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Efabless
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caravel_mram
caravel_mram PublicForked from efabless/caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Verilog
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caravel_demo
caravel_demo PublicForked from efabless/caravel_user_project
https://caravel-user-project.readthedocs.io
Verilog
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283 contributions in the last year
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Contribution activity
March 2025
Created 41 repositories
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jeffdi/cuprj-cli
Python
This contribution was made on Mar 14
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jeffdi/EF_PIN_MUX
Verilog
This contribution was made on Mar 4
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jeffdi/globalfoundries-pdk-libs-gf180mcu_f...
Jupyter Notebook
This contribution was made on Mar 4
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jeffdi/OpenFPGA_bitstream_generation
Verilog
This contribution was made on Mar 4
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jeffdi/mvcc-demo
Verilog
This contribution was made on Mar 4
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jeffdi/nydesign-demo
Verilog
This contribution was made on Mar 4
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jeffdi/caravel_mini
Verilog
This contribution was made on Mar 4
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jeffdi/OL-DFFRAM
Verilog
This contribution was made on Mar 4
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jeffdi/skywater-pdk-libs-sky130_fd_sc_hd
Verilog
This contribution was made on Mar 4
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jeffdi/skywater-pdk-libs-sky130_fd_pr
Python
This contribution was made on Mar 4
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jeffdi/skywater-pdk-libs-sky130_fd_io
Verilog
This contribution was made on Mar 4
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jeffdi/chipcraft---mest-course
TL-Verilog
This contribution was made on Mar 4
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jeffdi/EF_IP_UTIL
Verilog
This contribution was made on Mar 4
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jeffdi/EF_UVM
Python
This contribution was made on Mar 4
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jeffdi/caravel_mgmt_soc_litex
Verilog
This contribution was made on Mar 4
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jeffdi/sky130_klayout_pdk
Python
This contribution was made on Mar 4
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jeffdi/EF_USB_CDC_WRAPPER
Verilog
This contribution was made on Mar 4
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jeffdi/EF_I2S
Verilog
This contribution was made on Mar 4
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jeffdi/caravel_user_mini
Verilog
This contribution was made on Mar 4
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jeffdi/openframe_user_project
Verilog
This contribution was made on Mar 4
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jeffdi/volare
Python
This contribution was made on Mar 4
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jeffdi/EF_UART
Verilog
This contribution was made on Mar 4
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jeffdi/EF_I2C
Verilog
This contribution was made on Mar 4
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jeffdi/EF_SPI
Verilog
This contribution was made on Mar 4
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jeffdi/EF_TMR32
Verilog
This contribution was made on Mar 4
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jeffdi/ipm
Python
This contribution was made on Mar 4
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jeffdi/nix-eda
Nix
This contribution was made on Mar 4
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jeffdi/openlane2-ci-designs
Verilog
This contribution was made on Mar 4
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jeffdi/central_CI
This contribution was made on Mar 4
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jeffdi/caravel_SI_testing
C
This contribution was made on Mar 4
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jeffdi/openframe_timer_example
Verilog
This contribution was made on Mar 4
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jeffdi/Caravel_on_FPGA
Verilog
This contribution was made on Mar 4
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jeffdi/panamax
Verilog
This contribution was made on Mar 4
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jeffdi/chipignite_discover
HTML
This contribution was made on Mar 4
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jeffdi/openlane2
Python
This contribution was made on Mar 4
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jeffdi/IHP-Open-PDK
HTML
This contribution was made on Mar 4
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jeffdi/timing-scripts
Python
This contribution was made on Mar 4
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jeffdi/caravel_board
C
This contribution was made on Mar 4
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jeffdi/mpw_precheck
Python
This contribution was made on Mar 4
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jeffdi/caravel_user_project_analog
Verilog
This contribution was made on Mar 4
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jeffdi/caravel
Verilog
This contribution was made on Mar 4
16
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