Skip to content
View jeffdi's full-sized avatar

Block or report jeffdi

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. openfpga openfpga Public

    Forked from chiplicity/openfpga

    Verilog 1

  2. caravel_mram caravel_mram Public

    Forked from efabless/caravel_mpw-one

    Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

    Verilog

  3. caravel_demo caravel_demo Public

    Forked from efabless/caravel_user_project

    https://caravel-user-project.readthedocs.io

    Verilog

  4. zero_to_asic_mpw5 zero_to_asic_mpw5 Public

    Forked from mattvenn/zero_to_asic_mpw5

    Verilog

  5. my_project my_project Public

    Verilog

  6. hvcc_demo hvcc_demo Public

    Verilog

283 contributions in the last year

Contribution Graph
Day of Week March April May June July August September October November December January February March
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
Less
No contributions.
Low contributions.
Medium-low contributions.
Medium-high contributions.
High contributions.
More

Contribution activity

March 2025

16 repositories not shown
Loading