VLSI Physical Design Engineer specializing in floorplanning, placement, CTS, routing, and timing closure.
Passionate about ASIC design, automation scripts, and
- india
- in/jangamajay
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VLSI_PD_ORCA_TOP
VLSI_PD_ORCA_TOP PublicPD_ORCA_TOP_28nm demonstrated a complete block-level ASIC PnR flow using Synopsys ICC2, transforming gate-level netlist to GDSII across floorplanning, power planning, placement, CTS, routing, and s…
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