MXFP4 double buffer barrier fix #866
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Signed-off-by: Aurore De Spirlet <aurore.despirlet@amd.com>
Signed-off-by: Aurore De Spirlet <aurore.despirlet@amd.com>
Signed-off-by: Aurore De Spirlet <aurore.despirlet@amd.com>
Signed-off-by: Aurore De Spirlet <aurore.despirlet@amd.com>
Signed-off-by: Aurore De Spirlet <aurore.despirlet@amd.com>
Signed-off-by: Aurore De Spirlet <aurore.despirlet@amd.com>
IE rather than extracting an i8 (and bitcasting to f8e8m0fnu) from a 4x vector (IE one VGPR) to use as mfma argument, use the extraction offset as the opsel argument for the mfma. This should reduce register pressure. Signed-off-by: William G Hatch <william@hatch.uno>
Signed-off-by: William G Hatch <william@hatch.uno>
Signed-off-by: William G Hatch <william@hatch.uno>
Signed-off-by: William G Hatch <william@hatch.uno>
The speculative_decoding.py tests change because the extra canonicalize pass optimizes some things away. Eg. nested conditionals simplified to one conditional with a merged condition expression. The pipelined_attention.py changes are similar, it looks like double canonicalization merged some things which moved bits around and changed some counts. Signed-off-by: William G Hatch <william@hatch.uno>
Signed-off-by: William G Hatch <william@hatch.uno>
Signed-off-by: William G Hatch <william@hatch.uno>
Signed-off-by: Aurore De Spirlet <aurore.despirlet@amd.com>
Signed-off-by: Aurore De Spirlet <aurore.despirlet@amd.com>
panditsa
reviewed
Feb 20, 2026
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| """Double-buffered MXFP4 GEMM, 8 waves, with stagger.""" | ||
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| mlir = """ |
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Do we still need to pass the MLIR text entirely?
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This PR places barriers differently in the double buffered mfp4 gemm to reduce stalls observed in the trace.
The previous schedule utilized amdgpu.lds_barrier prior to the wavefront staggering branch. This forced an immediate s_waitcnt vmcnt(0), resulting in big stalls in the prologue. This "too early" LDS synchronization (vmcnt(0)) prevented the overlap of indexing logic with the in flight global memory loads.
To resolve this, I replaced the amdgpu.lds_barrier with a pure rocdl.s.barrier. And inside the loop I inserted a amdgpu.memory_counter_wait load(0) immediately before the first vector load from LDS.