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Enhancement/213 #218

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4aad688
Populating ipbus_bridges area; first version of ipbus CDC
dmnewbold Oct 28, 2022
f2e9378
Bug fixes and final testbench
dmnewbold Oct 29, 2022
24cd58e
Adding doc file for ipbus_clk_bridge
dmnewbold Oct 29, 2022
4f7dabd
Adding templates for axi stuff
dmnewbold Oct 29, 2022
f5f3acd
First version of ipb2axi
dmnewbold Oct 29, 2022
466d6d7
Fix to ipb2axi
dmnewbold Oct 29, 2022
82c2403
Fix to ipb2axi
dmnewbold Oct 29, 2022
072f3aa
Adding cleaner axi interface and wrappers
dmnewbold Oct 30, 2022
813e161
Adding tb design for ipbus axi
dmnewbold Oct 30, 2022
8f3976e
Adding axi4 register testbench design
dmnewbold Oct 30, 2022
5eae605
Adding testbench design for ipb2axi
dmnewbold Oct 31, 2022
4949daf
Adding comments, fixing small bugs
dmnewbold Oct 31, 2022
7fbb421
Bug fix in address mask
dmnewbold Nov 1, 2022
417c3e2
Fix to address mask fields
dmnewbold Nov 1, 2022
9c4e962
Bug fixes in axi interface
dmnewbold Nov 18, 2022
e1292f7
Bug fix in axi stuff
dmnewbold Nov 18, 2022
e3c96ca
Cleaning up axi4lite stuff
dmnewbold Dec 3, 2022
c7c3a52
Adding axi proto checker stuff
dmnewbold Dec 3, 2022
28a9ef4
Merge branch 'enhancement/213' of github.com:ipbus/ipbus-firmware int…
dmnewbold Dec 3, 2022
5473798
Fixing error in filename
dmnewbold Dec 3, 2022
9072177
Adding no-latch variant of axi2ipb
dmnewbold Feb 9, 2023
097a4c2
nolatch fix
dmnewbold Feb 9, 2023
34544c3
Pipelining fix
dmnewbold Feb 9, 2023
3cdb803
Debuggin
dmnewbold Feb 9, 2023
68e8374
Fix to axi2ipb
dmnewbold Feb 9, 2023
44384ea
Making no-latch variant the default for axi2ipb
dmnewbold Feb 9, 2023
d35fdee
Removed _nolatch postfix from bridge entity name.
alessandrothea Mar 7, 2023
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First version of ipb2axi
  • Loading branch information
dmnewbold committed Oct 29, 2022
commit f5f3acd221ae43d5b44e528d3ff379c1b9cfaabc
101 changes: 96 additions & 5 deletions components/ipbus_bridges/firmware/hdl/ipbus_ipb2axi4lite.vhd
Original file line number Diff line number Diff line change
@@ -1,3 +1,10 @@
-- ipbus_ipb2axi4lite
--
-- This block bridges ipbus to axi4lite, acting as an ipbus slave and an axi4lite master.
-- It always produces 32b aligned accesses on the axi4lite bus.
--
-- Dave Newbold, 29/10/22

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@@ -9,14 +16,15 @@ entity ipbus_ipb2axi4lite is
generic(
C_S_AXI_DATA_WIDTH: integer := 32;
C_S_AXI_ADDR_WIDTH: integer := 32;
ADDR_MASK: std_logic_vector(31 downto 0) := X"11111111";
ADDR_BASE: std_logic_vector(31 downto 0) := X"00000000"
AXI_ADDR_MASK: std_logic_vector(31 downto 0) := X"11111111";
AXI_ADDR_BASE: std_logic_vector(31 downto 0) := X"00000000"
);
port(
ipb_in: in ipb_wbus;
ipb_clk: in std_logic;
ipb_rst: in std_logic;
ipb_in: in ipb_wbus;
ipb_out: out ipb_rbus
s_axi_aclk: in std_logic;
s_axi_aresetn: in std_logic;
s_axi_aresetn: out std_logic;
s_axi_awaddr: out std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
s_axi_awprot: out std_logic_vector(2 downto 0);
s_axi_awvalid: out std_logic;
@@ -43,6 +51,89 @@ end ipbus_ipb2axi4lite;

architecture rtl of ipbus_ipb2axi4lite is

signal addr: std_logic_vector(31 downto 0);
signal axi_w_done, axi_r_done, new_cyc: std_logic;

begin

-- Address conversion

addr <= ipb_in.ipb_addr and ADDR_MASK or ADDR_BASE;

-- ipbus handshaking

axi_w_done <= (s_axi_bvalid and ipb_in.ipb_write and ipb_in.ipb_strobe);
axi_r_done <= (s_axi_rvalid and not ipb_in.ipb_write and ipb_in.ipb_strobe);
new_cyc <= axi_w_done or axi_r_done or not ipb_in.ipb_strobe;

ipb_out.ack <= '1' when (axi_w_done = '1' and s_axi_bresp = "00") or (axi_r_done = '1' and s_axi_rresp = "00") else '0';
ipb_out.err <= '1' when (axi_w_done = '1' and s_axi_bresp /= "00") or (axi_r_done = '1' and s_axi_rresp /= "00") else '0';

-- AW bus

s_axi_awaddr <= addr; -- Doesn't change during bus cycle
s_axi_awprot <= "00";

process(ipb_clk)
begin
if rising_edge(ipb_clk) then
if ipb_rst = '1' then
s_axi_awvalid <= '0';
elsif new_cyc = '1' then
s_axi_awvalid <= ipb_in.ipb_strobe and ipb_in.ipb_write;
elsif s_axi_awready = '1' then
s_axi_awvalid <= '0';
end if;
end if;
end process;

-- W bus

s_axi_wdata <= ipb_in.ipb_wdata; -- Doesn't change during cycle
s_axi_wstrb <= "1111";

process(ipb_clk)
begin
if rising_edge(ipb_clk) then
if ipb_rst = '1' then
s_axi_wvalid <= '0';
elsif new_cyc = '1' then
s_axi_wvalid <= ipb_in.ipb_strobe and ipb_in.ipb_write;
elsif s_axi_wready = '1' then
s_axi_wvalid <= '0';
end if;
end if;
end process;

-- B bus

s_axi_bready <= '1';

-- AR bus

s_axi_araddr <= addr;
s_axi_arprot <= "00";

process(ipb_clk)
begin
if rising_edge(ipb_clk) then
if ipb_rst = '1' then
s_axi_arvalid <= '0';
elsif new_cyc = '1' then
s_axi_arvalid <= ipb_in.ipb_strobe and not ipb_in.ipb_write;
elsif s_axi_arready = '1' then
s_axi_arvalid <= '0';
end if;
end if;
end process;

-- R bus

s_axi_rready <= '1';
ipb_out.ipb_rdata <= s_axi_rdata;

-- axi reset

s_axi_aresetn <= ipb_rst;

end rtl;
28 changes: 0 additions & 28 deletions components/ipbus_slaves/addr_table/ipbus_axi4lite_master.xml

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29 changes: 0 additions & 29 deletions components/ipbus_slaves/firmware/cfg/ipbus_drp_bridge.dep

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29 changes: 0 additions & 29 deletions components/ipbus_slaves/firmware/cfg/ipbus_emac_hostbus.dep

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