Permute the pass pipeline to coalesce before setting up the matmul

intel · Dec 6, 2024 · 7d8b99d · 7d8b99d
1 parent 281cfd0
commit 7d8b99d
Showing 1 changed file with 5 additions and 2 deletions.
diff --git a/third_party/intel/backend/compiler.py b/third_party/intel/backend/compiler.py
@@ -239,15 +239,18 @@ def make_ttgir(mod, metadata, opt, properties):
             return XPUBackend.AdvancedPath.make_ttgir(mod, metadata, opt)
 
         passes.ttir.add_convert_to_ttgpuir(pm, "xpu", opt.num_warps, opt.threads_per_warp, opt.num_ctas)
+        # optimize TTGIR
+        intel.passes.ttgpuir.add_coalesce(pm)
+        intel.passes.ttgpuir.add_remove_layout_conversions(pm)
+
         intel.passes.ttgpuir.add_accelerate_matmul(pm)
         intel.passes.ttgpuir.add_remove_layout_conversions(pm)
         intel.passes.ttgpuir.add_materialize_block_pointer(pm)
         if os.getenv("TRITON_INTEL_REWRITE_TENSOR_POINTER", "0") == "1":
             intel.passes.ttgpuir.add_rewrite_tensor_pointer(pm)
         intel.passes.ttgpuir.add_pipeline(pm, opt.num_stages, False)
 
-        intel.passes.ttgpuir.add_coalesce(pm)
-        intel.passes.ttgpuir.add_remove_layout_conversions(pm)
+
         passes.ttgpuir.add_optimize_thread_locality(pm)
         passes.ttgpuir.add_optimize_dot_operands(pm, True)
         passes.common.add_cse(pm)