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db
db
 
 
incremental_db
incremental_db
 
 
simulation/modelsim
simulation/modelsim
 
 
ECE2300.asm.rpt
ECE2300.asm.rpt
 
 
ECE2300.cdf
ECE2300.cdf
 
 
ECE2300.done
ECE2300.done
 
 
ECE2300.eda.rpt
ECE2300.eda.rpt
 
 
ECE2300.fit.rpt
ECE2300.fit.rpt
 
 
ECE2300.fit.smsg
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ECE2300.fit.summary
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ECE2300.flow.rpt
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ECE2300.jdi
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ECE2300.map.rpt
ECE2300.map.rpt
 
 
ECE2300.map.smsg
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ECE2300.map.summary
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ECE2300.pin
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ECE2300.sta.summary
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ECE2300_assignment_defaults.qdf
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ECE2300_nativelink_simulation.rpt
ECE2300_nativelink_simulation.rpt
 
 
README.md
README.md
 
 
adder.v
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alu.v
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c5_pin_model_dump.txt
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control.v
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cpu.v
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decoder.done
decoder.done
 
 
decoder.flow.rpt
decoder.flow.rpt
 
 
decoder.map.rpt
decoder.map.rpt
 
 
decoder.map.summary
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decoder.v
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decoder_nativelink_simulation.rpt
decoder_nativelink_simulation.rpt
 
 
decoder_test.v
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haltlogic.v
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lab5.qpf
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lab5_test.v
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logical.v
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var_clk.v
var_clk.v
 
 

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ECE2300---SingleCoreProcessor

This is an implementation of a single-cycle processor from scratch, written in Verilog. This was the final assignment for Cornell's ECE 2300 - Digital Logic and Computer Organization.

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