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repo: post-rebase fixes
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antoinevg committed Jan 6, 2025
1 parent d5fe3d2 commit c768ad8
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Showing 6 changed files with 40 additions and 38 deletions.
2 changes: 1 addition & 1 deletion luna_soc/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,4 +4,4 @@
# Copyright (c) 2023 Great Scott Gadgets <[email protected]>
# SPDX-License-Identifier: BSD-3-Clause

#from .top_level_cli import *
from .top_level_cli import *
10 changes: 5 additions & 5 deletions luna_soc/gateware/core/usb2/ep_control.py
Original file line number Diff line number Diff line change
Expand Up @@ -61,10 +61,10 @@ class Status(csr.Register, access="r"):
class Reset(csr.Register, access="w"):
""" Reset register
high: Local reset control for the SETUP handler; writing a '1' to this register clears
fifo: Local reset control for the SETUP handler; writing a '1' to this register clears
the handler state.
"""
high : csr.Field(csr.action.W, unsigned(1))
fifo : csr.Field(csr.action.W, unsigned(1))
_0 : csr.Field(csr.action.ResRAW0, unsigned(7))

class Data(csr.Register, access="r"):
Expand Down Expand Up @@ -125,7 +125,7 @@ def elaborate(self, platform):

# Logic condition for getting a new setup packet.
new_setup = token.new_token & token.is_setup
reset_requested = self._reset.f.high.w_stb & self._reset.f.high.w_data
reset_requested = self._reset.f.fifo.w_stb & self._reset.f.fifo.w_data
clear_fifo = new_setup | reset_requested

#
Expand Down Expand Up @@ -180,8 +180,8 @@ def elaborate(self, platform):
self.debug[0] .eq(token.new_token),
self.debug[1] .eq(token.is_setup),

self.debug[2] .eq(self._reset.f.high.w_stb),
self.debug[3] .eq(self._reset.f.high.w_data),
self.debug[2] .eq(self._reset.f.fifo.w_stb),
self.debug[3] .eq(self._reset.f.fifo.w_data),
self.debug[4] .eq(reset_requested),

self.debug[5] .eq(self._control.f.address.w_stb),
Expand Down
16 changes: 8 additions & 8 deletions luna_soc/gateware/core/usb2/ep_in.py
Original file line number Diff line number Diff line change
Expand Up @@ -91,9 +91,9 @@ class Status(csr.Register, access="r"):
class Reset(csr.Register, access="w"):
""" Reset register
high: A write to this field Clears the FIFO without transmitting.
fifo: A write to this field Clears the FIFO without transmitting.
"""
high : csr.Field(csr.action.W, unsigned(1)) # FIXME do not like name
fifo : csr.Field(csr.action.W, unsigned(1)) # FIXME do not like name
_1 : csr.Field(csr.action.ResRAW0, unsigned(7))

class Data(csr.Register, access="w"):
Expand Down Expand Up @@ -168,7 +168,7 @@ def elaborate(self, platform):
#

# Create our FIFO; and set it to be cleared whenever the user requests.
m.submodules.fifo = fifo = ResetInserter(self._reset.f.high.w_stb)(
m.submodules.fifo = fifo = ResetInserter(self._reset.f.fifo.w_stb)(
SyncFIFOBuffered(width=8, depth=self._max_packet_size)
)

Expand All @@ -182,7 +182,7 @@ def elaborate(self, platform):
bytes_in_fifo = Signal(range(0, self._max_packet_size + 1))

# If we're clearing the whole FIFO, reset our data count.
with m.If(self._reset.f.high.w_stb):
with m.If(self._reset.f.fifo.w_stb):
m.d.usb += bytes_in_fifo.eq(0)

# Keep track of our FIFO's data count as data is added or removed.
Expand Down Expand Up @@ -213,7 +213,7 @@ def elaborate(self, platform):
endpoint_nakked = Array(Signal() for _ in range(16))

# Clear our system state on reset.
with m.If(self._reset.f.high.w_stb):
with m.If(self._reset.f.fifo.w_stb):
for i in range(16):
m.d.usb += [
endpoint_stalled[i] .eq(0),
Expand Down Expand Up @@ -304,7 +304,7 @@ def elaborate(self, platform):
m.next = "PRIMED"

# Always return to IDLE on reset.
with m.If(self._reset.f.high.w_stb):
with m.If(self._reset.f.fifo.w_stb):
m.next = "IDLE"

# PRIMED -- our CPU has provided data, but we haven't been sent an IN token, yet.
Expand Down Expand Up @@ -334,7 +334,7 @@ def elaborate(self, platform):
m.d.comb += handshakes_out.nak.eq(1)

# Always return to IDLE on reset.
with m.If(self._reset.f.high.w_stb):
with m.If(self._reset.f.fifo.w_stb):
m.next = "IDLE"

# SEND_ZLP -- we're now now ready to respond to an IN token with a ZLP.
Expand Down Expand Up @@ -375,7 +375,7 @@ def elaborate(self, platform):
m.next = 'IDLE'

# Always return to IDLE on reset.
with m.If(self._reset.f.high.w_stb):
with m.If(self._reset.f.fifo.w_stb):
m.next = "IDLE"


Expand Down
29 changes: 14 additions & 15 deletions luna_soc/gateware/core/usb2/ep_out.py
Original file line number Diff line number Diff line change
Expand Up @@ -45,9 +45,9 @@ class Control(csr.Register, access="rw"):
class Endpoint(csr.Register, access="rw"):
""" Endpoint register
number: Selects the endpoint number to prime. This interface only allows priming a single endpoint
at once -- that is, only one endpoint can be ready to receive data at a time. See the
`enable` bit for usage.
number: Selects the endpoint number to prime. This interface allows priming multiple endpoints
at once. That is, multiple endpoints can be ready to receive data at a time. See the `prime`
and `enable` bits for usage.
"""
number : csr.Field(csr.action.RW, unsigned(4)) # desc="" ? # FIXME get around doubling RW registers?
_0 : csr.Field(csr.action.ResRAW0, unsigned(4))
Expand Down Expand Up @@ -115,9 +115,9 @@ class Status(csr.Register, access="r"):
class Reset(csr.Register, access="w"):
""" Reset register
high: Local reset for the OUT handler; clears the out FIFO.
fifo: Local reset for the OUT handler; clears the out FIFO.
"""
high : csr.Field(csr.action.W, unsigned(1))
fifo : csr.Field(csr.action.W, unsigned(1))
_0 : csr.Field(csr.action.ResRAW0, unsigned(7))

class Data(csr.Register, access="r"):
Expand Down Expand Up @@ -218,12 +218,11 @@ def elaborate(self, platform):
with m.If(self._prime.f.primed.w_stb):
m.d.usb += endpoint_primed[self._endpoint.f.number.data].eq(self._prime.f.primed.w_data)

# If we've just ACK'd a receive, clear our enable, un-prime the given endpoint and
# If we've just ACK'd a receive, clear our enable and
# clear our FIFO's ready state.
with m.If(interface.handshakes_out.ack & token.is_out):
m.d.usb += [
enabled .eq(0),
endpoint_primed[token.endpoint] .eq(0),
fifo_ready .eq(0),
]

Expand Down Expand Up @@ -251,7 +250,7 @@ def elaborate(self, platform):
#
# Core FIFO.
#
m.submodules.fifo = fifo = ResetInserter(self._reset.f.high.w_stb)(
m.submodules.fifo = fifo = ResetInserter(self._reset.f.fifo.w_stb)(
SyncFIFOBuffered(width=8, depth=self._max_packet_size)
)

Expand All @@ -260,16 +259,16 @@ def elaborate(self, platform):
# - We've primed the relevant endpoint.
# - Our most recent token is an OUT.
# - We're not stalled.
stalled = token.is_out & endpoint_stalled[token.endpoint]
endpoint_primed = endpoint_primed[token.endpoint]
ready_to_receive = fifo_ready & endpoint_primed & enabled & ~stalled
allow_receive = token.is_out & ready_to_receive
nak_receives = token.is_out & ~ready_to_receive & ~stalled
stalled = token.is_out & endpoint_stalled[token.endpoint]
is_endpoint_primed = endpoint_primed[token.endpoint]
ready_to_receive = fifo_ready & is_endpoint_primed & enabled & ~stalled
allow_receive = token.is_out & ready_to_receive
nak_receives = token.is_out & ~ready_to_receive & ~stalled

# Shortcut for when we have a "redundant"/incorrect PID. In these cases, we'll assume
# the host missed our ACK, and per the USB spec, implicitly ACK the packet.
is_redundant_pid = (interface.rx_pid_toggle != endpoint_data_pid[token.endpoint])
is_redundant_packet = endpoint_primed & token.is_out & is_redundant_pid
is_redundant_packet = is_endpoint_primed & token.is_out & is_redundant_pid

# Shortcut conditions under which we'll ACK and NAK a receive.
ack_redundant_packet = (is_redundant_packet & interface.rx_ready_for_response)
Expand Down Expand Up @@ -324,7 +323,7 @@ def elaborate(self, platform):

# debug
m.d.comb += [
self.debug[3] .eq(endpoint_primed),
self.debug[3] .eq(is_endpoint_primed),
self.debug[4] .eq(enabled),
#self.debug[5] .eq(token.is_out),
#self.debug[5] .eq(interface.rx_pid_toggle),
Expand Down
15 changes: 8 additions & 7 deletions luna_soc/generate/svd.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
import logging
import sys

from collections import defaultdict
Expand Down Expand Up @@ -82,14 +83,14 @@ def generate(self, file=None, vendor="luna-soc", name="soc", description=None):
# <peripherals />
peripherals = SubElement(device, "peripherals")
csr_base = self.csr_base
print(f"\ncsr_base: 0x{csr_base:08x}")
logging.debug(f"\ncsr_base: 0x{csr_base:08x}")
for name, resource_infos in self.csr_peripherals.items():
# so, in theory, these are always sorted so:
pstart = resource_infos[0].start
pend = resource_infos[-1].end

name = "_".join([str(s) for s in name]) if isinstance(name, tuple) else name[0]
print(f" {name} 0x{pstart:04x} => 0x{pend:04x} width: {pend - pstart} bytes")
logging.debug(f" {name} 0x{pstart:04x} => 0x{pend:04x} width: {pend - pstart} bytes")
peripheral = self._peripheral(peripherals, name, pstart + csr_base, pend + csr_base)

# <registers />
Expand All @@ -105,7 +106,7 @@ def generate(self, file=None, vendor="luna-soc", name="soc", description=None):
# description = {resource.__class__.__doc__}")
description = "TODO amaranth_soc/csr/reg.py:471"

print(f" {name}\t0x{rstart:02x} => 0x{rend:02x} width: {rend - rstart} bytes")
logging.debug(f" {name}\t0x{rstart:02x} => 0x{rend:02x} width: {rend - rstart} bytes")

register = self._register(
registers, # root
Expand All @@ -129,7 +130,7 @@ def generate(self, file=None, vendor="luna-soc", name="soc", description=None):

bitRange = "[{:d}:{:d}]".format(offset + width - 1, offset)

print(f" {name}\toffset:0x{offset} width: {width} bits range: {bitRange}")
logging.debug(f" {name}\toffset:0x{offset} width: {width} bits range: {bitRange}")

field = self._field(
fields, # root
Expand All @@ -142,11 +143,11 @@ def generate(self, file=None, vendor="luna-soc", name="soc", description=None):

offset += width

print("\nwishbone peripherals:")
logging.debug("\nwishbone peripherals:")
for name, t in self.wb_peripherals.items():
print(f"\t{name} => {t}")
logging.debug(f"\t{name} => {t}")

print("\n---------------\n")
logging.debug("\n---------------\n")

# generate output
output = ElementTree.tostring(device, 'utf-8')
Expand Down
6 changes: 4 additions & 2 deletions luna_soc/top_level_cli.py
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
from luna import configure_default_logging
from luna.gateware.platform import get_appropriate_platform, configure_toolchain

from luna_soc.generate import Generate, Introspect
#from luna_soc.generate import Generate, Introspect


def top_level_cli(fragment, *pos_args, **kwargs):
Expand Down Expand Up @@ -127,7 +127,9 @@ def top_level_cli(fragment, *pos_args, **kwargs):
# If we've been asked to generate a SVD description of the design, generate -only- that.
if args.generate_svd:
logging.info("Generating SVD description for SoC")
Generate(fragment.soc).svd(file=None)
#Generate(fragment.soc).svd(file=None)
from luna_soc.generate.svd import GenerateSVD
GenerateSVD(fragment).generate(file=None)
sys.exit(0)

# If we've been asked for the address firmware should be loaded, generate _only_ that.
Expand Down

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