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Fix crash on x86 when building with MSVC
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There is a compiler bug in latest MSVC, which at the time of writing is
19.36.32535: given `switch (x)`, where `x` is 64 bits wide, the compiler
generates code that computes an incorrect jump table index. E.g. if
`x` is zero, it ends up reading the table entry at index -1.
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@oleavr
oleavr committed Jan 18, 2024
1 parent 25a69b5 commit fc538eb
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Showing 15 changed files with 94 additions and 94 deletions.
14 changes: 7 additions & 7 deletions arch/AArch64/AArch64GenAsmWriter.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -16829,7 +16829,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
assert(Bits != 0 && "Cannot print this instruction.");

// Fragment 0 encoded into 7 bits for 78 unique commands.
switch ((Bits >> 14) & 127) {
switch ((uint32_t)((Bits >> 14) & 127)) {
default: assert(0 && "Invalid command number.");
case 0:
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
Expand Down Expand Up @@ -17339,7 +17339,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 1 encoded into 7 bits for 89 unique commands.
switch ((Bits >> 21) & 127) {
switch ((uint32_t)((Bits >> 21) & 127)) {
default: assert(0 && "Invalid command number.");
case 0:
// TLSDESCCALL, AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, ...
Expand Down Expand Up @@ -17790,7 +17790,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 2 encoded into 7 bits for 89 unique commands.
switch ((Bits >> 28) & 127) {
switch ((uint32_t)((Bits >> 28) & 127)) {
default: assert(0 && "Invalid command number.");
case 0:
// ABSWr, ABSXr, ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDG, ADDPL_XXI,...
Expand Down Expand Up @@ -18267,7 +18267,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 3 encoded into 7 bits for 128 unique commands.
switch ((Bits >> 35) & 127) {
switch ((uint32_t)((Bits >> 35) & 127)) {
default: assert(0 && "Invalid command number.");
case 0:
// ABSWr, ABSXr, ABSv1i64, AESIMC_ZZ_B, AESMC_ZZ_B, AUTDA, AUTDB, AUTIA, ...
Expand Down Expand Up @@ -18927,7 +18927,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 4 encoded into 7 bits for 88 unique commands.
switch ((Bits >> 42) & 127) {
switch ((uint32_t)((Bits >> 42) & 127)) {
default: assert(0 && "Invalid command number.");
case 0:
// ABS_ZPmZ_B, ADDHNB_ZZZ_H, ADD_VG2_2ZZ_D, ADD_VG2_2ZZ_H, ADD_VG2_2ZZ_S,...
Expand Down Expand Up @@ -19395,7 +19395,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 5 encoded into 7 bits for 88 unique commands.
switch ((Bits >> 49) & 127) {
switch ((uint32_t)((Bits >> 49) & 127)) {
default: assert(0 && "Invalid command number.");
case 0:
// ADCLB_ZZZ_D, ADCLB_ZZZ_S, ADCLT_ZZZ_D, ADCLT_ZZZ_S, ADCSWr, ADCSXr, AD...
Expand Down Expand Up @@ -19862,7 +19862,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 6 encoded into 6 bits for 44 unique commands.
switch ((Bits >> 56) & 63) {
switch ((uint32_t)((Bits >> 56) & 63)) {
default: assert(0 && "Invalid command number.");
case 0:
// ADDG, ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, A...
Expand Down
16 changes: 8 additions & 8 deletions arch/ARM/ARMGenAsmWriter.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -9634,7 +9634,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
assert(Bits != 0 && "Cannot print this instruction.");

// Fragment 0 encoded into 6 bits for 43 unique commands.
switch ((Bits >> 13) & 63) {
switch ((uint32_t)((Bits >> 13) & 63)) {
default:
assert(0 && "Invalid command number.");
case 0:
Expand Down Expand Up @@ -9860,7 +9860,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
}

// Fragment 1 encoded into 7 bits for 89 unique commands.
switch ((Bits >> 19) & 127) {
switch ((uint32_t)((Bits >> 19) & 127)) {
default:
assert(0 && "Invalid command number.");
case 0:
Expand Down Expand Up @@ -10462,7 +10462,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
}

// Fragment 2 encoded into 7 bits for 69 unique commands.
switch ((Bits >> 26) & 127) {
switch ((uint32_t)((Bits >> 26) & 127)) {
default:
assert(0 && "Invalid command number.");
case 0:
Expand Down Expand Up @@ -10877,7 +10877,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
}

// Fragment 3 encoded into 6 bits for 39 unique commands.
switch ((Bits >> 33) & 63) {
switch ((uint32_t)((Bits >> 33) & 63)) {
default:
assert(0 && "Invalid command number.");
case 0:
Expand Down Expand Up @@ -11085,7 +11085,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
}

// Fragment 4 encoded into 7 bits for 77 unique commands.
switch ((Bits >> 39) & 127) {
switch ((uint32_t)((Bits >> 39) & 127)) {
default:
assert(0 && "Invalid command number.");
case 0:
Expand Down Expand Up @@ -11527,7 +11527,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
}

// Fragment 5 encoded into 5 bits for 27 unique commands.
switch ((Bits >> 46) & 31) {
switch ((uint32_t)((Bits >> 46) & 31)) {
default:
assert(0 && "Invalid command number.");
case 0:
Expand Down Expand Up @@ -11689,7 +11689,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
}

// Fragment 6 encoded into 6 bits for 38 unique commands.
switch ((Bits >> 51) & 63) {
switch ((uint32_t)((Bits >> 51) & 63)) {
default:
assert(0 && "Invalid command number.");
case 0:
Expand Down Expand Up @@ -11897,7 +11897,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O)
}

// Fragment 7 encoded into 4 bits for 16 unique commands.
switch ((Bits >> 57) & 15) {
switch ((uint32_t)((Bits >> 57) & 15)) {
default:
assert(0 && "Invalid command number.");
case 0:
Expand Down
8 changes: 4 additions & 4 deletions arch/Alpha/AlphaGenAsmWriter.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -1221,7 +1221,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
assert(Bits != 0 && "Cannot print this instruction.");

// Fragment 0 encoded into 3 bits for 5 unique commands.
switch ((Bits >> 11) & 7) {
switch ((uint32_t)((Bits >> 11) & 7)) {
default: assert(0 && "Invalid command number.");
case 0:
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
Expand Down Expand Up @@ -1252,7 +1252,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 1 encoded into 4 bits for 13 unique commands.
switch ((Bits >> 14) & 15) {
switch ((uint32_t)((Bits >> 14) & 15)) {
default: assert(0 && "Invalid command number.");
case 0:
// ADJUSTSTACKDOWN, ADJUSTSTACKUP, BR, RC, RPCC, RS
Expand Down Expand Up @@ -1343,7 +1343,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 2 encoded into 2 bits for 4 unique commands.
switch ((Bits >> 18) & 3) {
switch ((uint32_t)((Bits >> 18) & 3)) {
default: assert(0 && "Invalid command number.");
case 0:
// ADDLi, ADDLr, ADDQi, ADDQr, ADDS, ADDT, ANDi, ANDr, BICi, BICr, BISi, ...
Expand All @@ -1369,7 +1369,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 3 encoded into 3 bits for 6 unique commands.
switch ((Bits >> 20) & 7) {
switch ((uint32_t)((Bits >> 20) & 7)) {
default: assert(0 && "Invalid command number.");
case 0:
// ADDLi, ADDLr, ADDQi, ADDQr, ADDS, ADDT, ANDi, ANDr, BICi, BICr, BISi, ...
Expand Down
12 changes: 6 additions & 6 deletions arch/Mips/MipsGenAsmWriter.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4703,7 +4703,7 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)

// Fragment 0 encoded into 4 bits for 11 unique commands.
//printf("Frag-0: %"PRIu64"\n", (Bits >> 14) & 15);
switch ((Bits >> 14) & 15) {
switch ((uint32_t)((Bits >> 14) & 15)) {
default: // llvm_unreachable("Invalid command number.");
case 0:
// DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, Break16, CONSTPOOL_EN...
Expand Down Expand Up @@ -4765,7 +4765,7 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)

// Fragment 1 encoded into 5 bits for 17 unique commands.
//printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 31);
switch ((Bits >> 18) & 31) {
switch ((uint32_t)((Bits >> 18) & 31)) {
default: // llvm_unreachable("Invalid command number.");
case 0:
// ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM...
Expand Down Expand Up @@ -4865,7 +4865,7 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)

// Fragment 2 encoded into 4 bits for 12 unique commands.
//printf("Frag-2: %"PRIu64"\n", (Bits >> 23) & 15);
switch ((Bits >> 23) & 15) {
switch ((uint32_t)((Bits >> 23) & 15)) {
default: // llvm_unreachable("Invalid command number.");
case 0:
// ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADD, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM...
Expand Down Expand Up @@ -4938,7 +4938,7 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)

// Fragment 3 encoded into 4 bits for 15 unique commands.
//printf("Frag-3: %"PRIu64"\n", (Bits >> 27) & 15);
switch ((Bits >> 27) & 15) {
switch ((uint32_t)((Bits >> 27) & 15)) {
default: // llvm_unreachable("Invalid command number.");
case 0:
// ABSQ_S_PH, ABSQ_S_QB, ABSQ_S_W, ADDIUPC, ADDIUPC_MM, ADDIUR1SP_MM, ALU...
Expand Down Expand Up @@ -5033,7 +5033,7 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)

// Fragment 4 encoded into 3 bits for 5 unique commands.
//printf("Frag-4: %"PRIu64"\n", (Bits >> 31) & 7);
switch ((Bits >> 31) & 7) {
switch ((uint32_t)((Bits >> 31) & 7)) {
default: // llvm_unreachable("Invalid command number.");
case 0:
// ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD...
Expand All @@ -5060,7 +5060,7 @@ static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)

// Fragment 5 encoded into 2 bits for 3 unique commands.
//printf("Frag-5: %"PRIu64"\n", (Bits >> 34) & 3);
switch ((Bits >> 34) & 3) {
switch ((uint32_t)((Bits >> 34) & 3)) {
default: // llvm_unreachable("Invalid command number.");
case 0:
// ADD, ADDIUR2_MM, ADDQH_PH, ADDQH_R_PH, ADDQH_R_W, ADDQH_W, ADDQ_PH, AD...
Expand Down
22 changes: 11 additions & 11 deletions arch/PowerPC/PPCGenAsmWriter.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10473,7 +10473,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
assert(Bits != 0 && "Cannot print this instruction.");

// Fragment 0 encoded into 5 bits for 22 unique commands.
switch ((Bits >> 15) & 31) {
switch ((uint32_t)((Bits >> 15) & 31)) {
default: assert(0 && "Invalid command number.");
case 0:
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
Expand Down Expand Up @@ -10604,7 +10604,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 1 encoded into 5 bits for 24 unique commands.
switch ((Bits >> 20) & 31) {
switch ((uint32_t)((Bits >> 20) & 31)) {
default: assert(0 && "Invalid command number.");
case 0:
// BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL...
Expand Down Expand Up @@ -10758,7 +10758,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 2 encoded into 5 bits for 31 unique commands.
switch ((Bits >> 25) & 31) {
switch ((uint32_t)((Bits >> 25) & 31)) {
default: assert(0 && "Invalid command number.");
case 0:
// BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL...
Expand Down Expand Up @@ -10929,7 +10929,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 3 encoded into 3 bits for 6 unique commands.
switch ((Bits >> 30) & 7) {
switch ((uint32_t)((Bits >> 30) & 7)) {
default: assert(0 && "Invalid command number.");
case 0:
// BUILD_UACC, DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, ADDME, ADDME8, ADDME8O...
Expand Down Expand Up @@ -10967,7 +10967,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 4 encoded into 5 bits for 23 unique commands.
switch ((Bits >> 33) & 31) {
switch ((uint32_t)((Bits >> 33) & 31)) {
default: assert(0 && "Invalid command number.");
case 0:
// CLRLSLDI, CLRLSLDI_rec, CLRRDI, CLRRDI_rec, EXTLDI, EXTLDI_rec, EXTRDI...
Expand Down Expand Up @@ -11089,7 +11089,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 5 encoded into 2 bits for 4 unique commands.
switch ((Bits >> 38) & 3) {
switch ((uint32_t)((Bits >> 38) & 3)) {
default: assert(0 && "Invalid command number.");
case 0:
// CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, EXTLDI, EXTLDI_rec, EX...
Expand All @@ -11113,7 +11113,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 6 encoded into 4 bits for 11 unique commands.
switch ((Bits >> 40) & 15) {
switch ((uint32_t)((Bits >> 40) & 15)) {
default: assert(0 && "Invalid command number.");
case 0:
// CLRLSLDI, CLRLSLDI_rec, EXTLDI, EXTLDI_rec, EXTRDI, EXTRDI_rec, INSRDI...
Expand Down Expand Up @@ -11170,7 +11170,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 7 encoded into 2 bits for 4 unique commands.
switch ((Bits >> 44) & 3) {
switch ((uint32_t)((Bits >> 44) & 3)) {
default: assert(0 && "Invalid command number.");
case 0:
// CLRLSLWI, CLRLSLWI_rec, EXTLWI, EXTLWI_rec, EXTRWI, EXTRWI_rec, INSLWI...
Expand All @@ -11193,7 +11193,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 8 encoded into 3 bits for 7 unique commands.
switch ((Bits >> 46) & 7) {
switch ((uint32_t)((Bits >> 46) & 7)) {
default: assert(0 && "Invalid command number.");
case 0:
// PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVF32GER, PM...
Expand Down Expand Up @@ -11231,7 +11231,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 9 encoded into 3 bits for 5 unique commands.
switch ((Bits >> 49) & 7) {
switch ((uint32_t)((Bits >> 49) & 7)) {
default: assert(0 && "Invalid command number.");
case 0:
// PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVI16GER2, P...
Expand Down Expand Up @@ -11260,7 +11260,7 @@ static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {


// Fragment 10 encoded into 2 bits for 3 unique commands.
switch ((Bits >> 52) & 3) {
switch ((uint32_t)((Bits >> 52) & 3)) {
default: assert(0 && "Invalid command number.");
case 0:
// PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVI16GER2, P...
Expand Down
8 changes: 4 additions & 4 deletions arch/RISCV/RISCVGenAsmWriter.inc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1197,7 +1197,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)


// Fragment 0 encoded into 2 bits for 4 unique commands.
switch ((Bits >> 12) & 3) {
switch ((uint32_t)((Bits >> 12) & 3)) {
default: CS_ASSERT(0 && "Invalid command number.");
case 0:
// DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL...
Expand Down Expand Up @@ -1225,7 +1225,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)


// Fragment 1 encoded into 2 bits for 3 unique commands.
switch ((Bits >> 14) & 3) {
switch ((uint32_t)((Bits >> 14) & 3)) {
default: CS_ASSERT(0 && "Invalid command number.");
case 0:
// PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR
Expand All @@ -1246,7 +1246,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)


// Fragment 2 encoded into 2 bits for 3 unique commands.
switch ((Bits >> 16) & 3) {
switch ((uint32_t)((Bits >> 16) & 3)) {
default: CS_ASSERT(0 && "Invalid command number.");
case 0:
// PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP...
Expand All @@ -1267,7 +1267,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)


// Fragment 3 encoded into 2 bits for 4 unique commands.
switch ((Bits >> 18) & 3) {
switch ((uint32_t)((Bits >> 18) & 3)) {
default: CS_ASSERT(0 && "Invalid command number.");
case 0:
// PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M...
Expand Down
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