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Preparation for IDF v5.5 and ESP32-C5 #10884

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Preparation for IDF v5.5 and ESP32-C5 #10884

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f46725e
feat(idf): Add initial support for IDF v5.5 and ESP32-C5
me-no-dev Jan 21, 2025
41d179e
fix(examples): Add changes required to some examples
me-no-dev Jan 21, 2025
3ac1e5b
fix(examples): Disable CI for ESP32 on RMakerSonoffDualR3
me-no-dev Jan 22, 2025
b9d6ce3
fix(c5): Update bootloader location
me-no-dev Jan 22, 2025
bfe6f74
fix(report): Add missing chip names
me-no-dev Jan 22, 2025
def86ec
fix(c5): Update debug log in setCpuFrequencyMhz
P-R-O-C-H-Y Jan 22, 2025
44e0e70
add c5 bootloader location to pioarduino script (#10889)
Jason2866 Jan 22, 2025
4e9dec5
fix(ci): Fix/stop some examples for C5
me-no-dev Jan 22, 2025
09de42a
fix(c5): Update PIN_RGB_LED in pins_arduino.h
P-R-O-C-H-Y Jan 22, 2025
28bf580
fix(psram): Add support for ESP32-C5 PSRAM
me-no-dev Jan 27, 2025
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2 changes: 1 addition & 1 deletion CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
# idf.py build

set(min_supported_idf_version "5.3.0")
set(max_supported_idf_version "5.4.99")
set(max_supported_idf_version "5.5.99")
set(idf_version "${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}.${IDF_VERSION_PATCH}")

if ("${idf_version}" AND NOT "$ENV{ARDUINO_SKIP_IDF_VERSION_CHECK}")
Expand Down
217 changes: 217 additions & 0 deletions boards.txt
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Expand Up @@ -161,6 +161,223 @@ esp32c2.menu.EraseFlash.all.upload.erase_cmd=-e

##############################################################

esp32c5.name=ESP32C5 Dev Module

esp32c5.bootloader.tool=esptool_py
esp32c5.bootloader.tool.default=esptool_py

esp32c5.upload.tool=esptool_py
esp32c5.upload.tool.default=esptool_py
esp32c5.upload.tool.network=esp_ota

esp32c5.upload.maximum_size=1310720
esp32c5.upload.maximum_data_size=327680
esp32c5.upload.flags=
esp32c5.upload.extra_flags=
esp32c5.upload.use_1200bps_touch=false
esp32c5.upload.wait_for_upload_port=false

esp32c5.serial.disableDTR=false
esp32c5.serial.disableRTS=false

esp32c5.build.tarch=riscv32
esp32c5.build.target=esp
esp32c5.build.mcu=esp32c5
esp32c5.build.core=esp32
esp32c5.build.variant=esp32c5
esp32c5.build.board=ESP32C5_DEV
esp32c5.build.bootloader_addr=0x2000

esp32c5.build.cdc_on_boot=0
esp32c5.build.f_cpu=240000000L
esp32c5.build.flash_size=4MB
esp32c5.build.flash_freq=80m
esp32c5.build.flash_mode=qio
esp32c5.build.boot=qio
esp32c5.build.partitions=default
esp32c5.build.defines=

## IDE 2.0 Seems to not update the value
esp32c5.menu.JTAGAdapter.default=Disabled
esp32c5.menu.JTAGAdapter.default.build.copy_jtag_files=0
esp32c5.menu.JTAGAdapter.builtin=Integrated USB JTAG
esp32c5.menu.JTAGAdapter.builtin.build.openocdscript=esp32c5-builtin.cfg
esp32c5.menu.JTAGAdapter.builtin.build.copy_jtag_files=1
esp32c5.menu.JTAGAdapter.external=FTDI Adapter
esp32c5.menu.JTAGAdapter.external.build.openocdscript=esp32c5-ftdi.cfg
esp32c5.menu.JTAGAdapter.external.build.copy_jtag_files=1
esp32c5.menu.JTAGAdapter.bridge=ESP USB Bridge
esp32c5.menu.JTAGAdapter.bridge.build.openocdscript=esp32c5-bridge.cfg
esp32c5.menu.JTAGAdapter.bridge.build.copy_jtag_files=1

esp32c5.menu.PSRAM.disabled=Disabled
esp32c5.menu.PSRAM.disabled.build.defines=
esp32c5.menu.PSRAM.enabled=Enabled
esp32c5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM

esp32c5.menu.CDCOnBoot.default=Disabled
esp32c5.menu.CDCOnBoot.default.build.cdc_on_boot=0
esp32c5.menu.CDCOnBoot.cdc=Enabled
esp32c5.menu.CDCOnBoot.cdc.build.cdc_on_boot=1

esp32c5.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
esp32c5.menu.PartitionScheme.default.build.partitions=default
esp32c5.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
esp32c5.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
esp32c5.menu.PartitionScheme.default_8MB=8M with spiffs (3MB APP/1.5MB SPIFFS)
esp32c5.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
esp32c5.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
esp32c5.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
esp32c5.menu.PartitionScheme.minimal.build.partitions=minimal
esp32c5.menu.PartitionScheme.no_fs=No FS 4MB (2MB APP x2)
esp32c5.menu.PartitionScheme.no_fs.build.partitions=no_fs
esp32c5.menu.PartitionScheme.no_fs.upload.maximum_size=2031616
esp32c5.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
esp32c5.menu.PartitionScheme.no_ota.build.partitions=no_ota
esp32c5.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
esp32c5.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
esp32c5.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
esp32c5.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
esp32c5.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
esp32c5.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
esp32c5.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
esp32c5.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
esp32c5.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
esp32c5.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
esp32c5.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
esp32c5.menu.PartitionScheme.huge_app.build.partitions=huge_app
esp32c5.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
esp32c5.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
esp32c5.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
esp32c5.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
esp32c5.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FATFS)
esp32c5.menu.PartitionScheme.fatflash.build.partitions=ffat
esp32c5.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
esp32c5.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9.9MB FATFS)
esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
esp32c5.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
esp32c5.menu.PartitionScheme.rainmaker=RainMaker 4MB
esp32c5.menu.PartitionScheme.rainmaker.build.partitions=rainmaker
esp32c5.menu.PartitionScheme.rainmaker.upload.maximum_size=1966080
esp32c5.menu.PartitionScheme.rainmaker_4MB=RainMaker 4MB No OTA
esp32c5.menu.PartitionScheme.rainmaker_4MB.build.partitions=rainmaker_4MB_no_ota
esp32c5.menu.PartitionScheme.rainmaker_4MB.upload.maximum_size=4038656
esp32c5.menu.PartitionScheme.rainmaker_8MB=RainMaker 8MB
esp32c5.menu.PartitionScheme.rainmaker_8MB.build.partitions=rainmaker_8MB
esp32c5.menu.PartitionScheme.rainmaker_8MB.upload.maximum_size=4116480
esp32c5.menu.PartitionScheme.zigbee_2MB=Zigbee 2MB with spiffs
esp32c5.menu.PartitionScheme.zigbee_2MB.build.partitions=zigbee_2MB
esp32c5.menu.PartitionScheme.zigbee_2MB.upload.maximum_size=1310720
esp32c5.menu.PartitionScheme.zigbee=Zigbee 4MB with spiffs
esp32c5.menu.PartitionScheme.zigbee.build.partitions=zigbee
esp32c5.menu.PartitionScheme.zigbee.upload.maximum_size=1310720
esp32c5.menu.PartitionScheme.zigbee_8MB=Zigbee 8MB with spiffs
esp32c5.menu.PartitionScheme.zigbee_8MB.build.partitions=zigbee_8MB
esp32c5.menu.PartitionScheme.zigbee_8MB.upload.maximum_size=3407872
esp32c5.menu.PartitionScheme.zigbee_zczr_2MB=Zigbee ZCZR 2MB with spiffs
esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.build.partitions=zigbee_zczr_2MB
esp32c5.menu.PartitionScheme.zigbee_zczr_2MB.upload.maximum_size=1310720
esp32c5.menu.PartitionScheme.zigbee_zczr=Zigbee ZCZR 4MB with spiffs
esp32c5.menu.PartitionScheme.zigbee_zczr.build.partitions=zigbee_zczr
esp32c5.menu.PartitionScheme.zigbee_zczr.upload.maximum_size=1310720
esp32c5.menu.PartitionScheme.zigbee_zczr_8MB=Zigbee ZCZR 8MB with spiffs
esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.build.partitions=zigbee_zczr_8MB
esp32c5.menu.PartitionScheme.zigbee_zczr_8MB.upload.maximum_size=3407872
esp32c5.menu.PartitionScheme.custom=Custom
esp32c5.menu.PartitionScheme.custom.build.partitions=
esp32c5.menu.PartitionScheme.custom.upload.maximum_size=16777216

esp32c5.menu.CPUFreq.240=240MHz (WiFi)
esp32c5.menu.CPUFreq.240.build.f_cpu=240000000L
esp32c5.menu.CPUFreq.120=120MHz (WiFi)
esp32c5.menu.CPUFreq.120.build.f_cpu=120000000L
esp32c5.menu.CPUFreq.80=80MHz (WiFi)
esp32c5.menu.CPUFreq.80.build.f_cpu=80000000L
esp32c5.menu.CPUFreq.40=40MHz
esp32c5.menu.CPUFreq.40.build.f_cpu=40000000L
esp32c5.menu.CPUFreq.20=20MHz
esp32c5.menu.CPUFreq.20.build.f_cpu=20000000L
esp32c5.menu.CPUFreq.10=10MHz
esp32c5.menu.CPUFreq.10.build.f_cpu=10000000L

esp32c5.menu.FlashMode.qio=QIO
esp32c5.menu.FlashMode.qio.build.flash_mode=dio
esp32c5.menu.FlashMode.qio.build.boot=qio
esp32c5.menu.FlashMode.dio=DIO
esp32c5.menu.FlashMode.dio.build.flash_mode=dio
esp32c5.menu.FlashMode.dio.build.boot=dio

esp32c5.menu.FlashFreq.80=80MHz
esp32c5.menu.FlashFreq.80.build.flash_freq=80m
esp32c5.menu.FlashFreq.40=40MHz
esp32c5.menu.FlashFreq.40.build.flash_freq=40m

esp32c5.menu.FlashSize.4M=4MB (32Mb)
esp32c5.menu.FlashSize.4M.build.flash_size=4MB
esp32c5.menu.FlashSize.8M=8MB (64Mb)
esp32c5.menu.FlashSize.8M.build.flash_size=8MB
esp32c5.menu.FlashSize.2M=2MB (16Mb)
esp32c5.menu.FlashSize.2M.build.flash_size=2MB
esp32c5.menu.FlashSize.16M=16MB (128Mb)
esp32c5.menu.FlashSize.16M.build.flash_size=16MB

esp32c5.menu.UploadSpeed.921600=921600
esp32c5.menu.UploadSpeed.921600.upload.speed=921600
esp32c5.menu.UploadSpeed.115200=115200
esp32c5.menu.UploadSpeed.115200.upload.speed=115200
esp32c5.menu.UploadSpeed.256000.windows=256000
esp32c5.menu.UploadSpeed.256000.upload.speed=256000
esp32c5.menu.UploadSpeed.230400.windows.upload.speed=256000
esp32c5.menu.UploadSpeed.230400=230400
esp32c5.menu.UploadSpeed.230400.upload.speed=230400
esp32c5.menu.UploadSpeed.460800.linux=460800
esp32c5.menu.UploadSpeed.460800.macosx=460800
esp32c5.menu.UploadSpeed.460800.upload.speed=460800
esp32c5.menu.UploadSpeed.512000.windows=512000
esp32c5.menu.UploadSpeed.512000.upload.speed=512000

esp32c5.menu.DebugLevel.none=None
esp32c5.menu.DebugLevel.none.build.code_debug=0
esp32c5.menu.DebugLevel.error=Error
esp32c5.menu.DebugLevel.error.build.code_debug=1
esp32c5.menu.DebugLevel.warn=Warn
esp32c5.menu.DebugLevel.warn.build.code_debug=2
esp32c5.menu.DebugLevel.info=Info
esp32c5.menu.DebugLevel.info.build.code_debug=3
esp32c5.menu.DebugLevel.debug=Debug
esp32c5.menu.DebugLevel.debug.build.code_debug=4
esp32c5.menu.DebugLevel.verbose=Verbose
esp32c5.menu.DebugLevel.verbose.build.code_debug=5

esp32c5.menu.EraseFlash.none=Disabled
esp32c5.menu.EraseFlash.none.upload.erase_cmd=
esp32c5.menu.EraseFlash.all=Enabled
esp32c5.menu.EraseFlash.all.upload.erase_cmd=-e

esp32c5.menu.ZigbeeMode.default=Disabled
esp32c5.menu.ZigbeeMode.default.build.zigbee_mode=
esp32c5.menu.ZigbeeMode.default.build.zigbee_libs=
esp32c5.menu.ZigbeeMode.ed=Zigbee ED (end device)
esp32c5.menu.ZigbeeMode.ed.build.zigbee_mode=-DZIGBEE_MODE_ED
esp32c5.menu.ZigbeeMode.ed.build.zigbee_libs=-lesp_zb_api_ed -lesp_zb_cli_command -lzboss_stack.ed -lzboss_port
esp32c5.menu.ZigbeeMode.zczr=Zigbee ZCZR (coordinator/router)
esp32c5.menu.ZigbeeMode.zczr.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
esp32c5.menu.ZigbeeMode.zczr.build.zigbee_libs=-lesp_zb_api_zczr -lesp_zb_cli_command -lzboss_stack.zczr -lzboss_port
esp32c5.menu.ZigbeeMode.rcp=Zigbee RCP (radio co-processor)
esp32c5.menu.ZigbeeMode.rcp.build.zigbee_mode=-DZIGBEE_MODE_RCP
esp32c5.menu.ZigbeeMode.rcp.build.zigbee_libs=-lesp_zb_api_rcp -lesp_zb_cli_command -lzboss_stack.rcp -lzboss_port
esp32c5.menu.ZigbeeMode.ed_debug=Zigbee ED (end device) - Debug
esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_mode=-DZIGBEE_MODE_ED
esp32c5.menu.ZigbeeMode.ed_debug.build.zigbee_libs=-lesp_zb_api_ed.debug -lesp_zb_cli_command -lzboss_stack.ed.debug -lzboss_port.debug
esp32c5.menu.ZigbeeMode.zczr_debug=Zigbee ZCZR (coordinator/router) - Debug
esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_mode=-DZIGBEE_MODE_ZCZR
esp32c5.menu.ZigbeeMode.zczr_debug.build.zigbee_libs=-lesp_zb_api_zczr.debug -lesp_zb_cli_command -lzboss_stack.zczr.debug -lzboss_port.debug
esp32c5.menu.ZigbeeMode.rcp_debug=Zigbee RCP (radio co-processor) - Debug
esp32c5.menu.ZigbeeMode.rcp_debug.build.zigbee_mode=-DZIGBEE_MODE_RCP
esp32c5.menu.ZigbeeMode.rcp_debug.build.zigbee_libs=-lesp_zb_api_rcp.debug -lesp_zb_cli_command -lzboss_stack.rcp.debug -lzboss_port.debug

##############################################################

esp32p4.name=ESP32P4 Dev Module

esp32p4.bootloader.tool=esptool_py
Expand Down
9 changes: 9 additions & 0 deletions cores/esp32/Esp.cpp
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Expand Up @@ -21,6 +21,7 @@
#include "Esp.h"
#include "esp_sleep.h"
#include "spi_flash_mmap.h"
#include "esp_idf_version.h"
#include <memory>
#include <soc/soc.h>
#include <esp_partition.h>
Expand Down Expand Up @@ -63,6 +64,9 @@ extern "C" {
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x2000 // Esp32p4 is located at 0x2000
#elif CONFIG_IDF_TARGET_ESP32C5
#include "esp32c5/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c5 is located at 0x0000
#else
#error Target CONFIG_IDF_TARGET is not supported
#endif
Expand Down Expand Up @@ -301,6 +305,11 @@ const char *EspClass::getChipModel(void) {
case CHIP_ESP32C6: return "ESP32-C6";
case CHIP_ESP32H2: return "ESP32-H2";
case CHIP_ESP32P4: return "ESP32-P4";
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0)
case CHIP_ESP32C5: return "ESP32-C5";
case CHIP_ESP32C61: return "ESP32-C61";
case CHIP_ESP32H21: return "ESP32-H21";
#endif
default: return "UNKNOWN";
}
#endif
Expand Down
8 changes: 8 additions & 0 deletions cores/esp32/HardwareSerial.h
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Expand Up @@ -127,6 +127,8 @@ typedef enum {
#define SOC_RX0 (gpio_num_t)23
#elif CONFIG_IDF_TARGET_ESP32P4
#define SOC_RX0 (gpio_num_t)38
#elif CONFIG_IDF_TARGET_ESP32C5
#define SOC_RX0 (gpio_num_t)12
#endif
#endif

Expand All @@ -145,6 +147,8 @@ typedef enum {
#define SOC_TX0 (gpio_num_t)24
#elif CONFIG_IDF_TARGET_ESP32P4
#define SOC_TX0 (gpio_num_t)37
#elif CONFIG_IDF_TARGET_ESP32C5
#define SOC_TX0 (gpio_num_t)11
#endif
#endif

Expand All @@ -168,6 +172,8 @@ typedef enum {
#define RX1 (gpio_num_t)0
#elif CONFIG_IDF_TARGET_ESP32P4
#define RX1 (gpio_num_t)11
#elif CONFIG_IDF_TARGET_ESP32C5
#define RX1 (gpio_num_t)4
#endif
#endif

Expand All @@ -188,6 +194,8 @@ typedef enum {
#define TX1 (gpio_num_t)1
#elif CONFIG_IDF_TARGET_ESP32P4
#define TX1 (gpio_num_t)10
#elif CONFIG_IDF_TARGET_ESP32C5
#define TX1 (gpio_num_t)5
#endif
#endif
#endif /* SOC_UART_HP_NUM > 1 */
Expand Down
8 changes: 8 additions & 0 deletions cores/esp32/chip-debug-report.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,9 @@ static void printPkgVersion(void) {
#elif CONFIG_IDF_TARGET_ESP32P4
uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_2_REG, EFUSE_PKG_VERSION);
chip_report_printf("%lu", pkg_ver);
#elif CONFIG_IDF_TARGET_ESP32C5
uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS2_REG, EFUSE_PKG_VERSION);
chip_report_printf("%lu", pkg_ver);
#else
chip_report_printf("Unknown");
#endif
Expand All @@ -88,6 +91,11 @@ static void printChipInfo(void) {
case CHIP_ESP32C6: chip_report_printf("ESP32-C6\n"); break;
case CHIP_ESP32H2: chip_report_printf("ESP32-H2\n"); break;
case CHIP_ESP32P4: chip_report_printf("ESP32-P4\n"); break;
#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 5, 0)
case CHIP_ESP32C5: chip_report_printf("ESP32-C5\n"); break;
case CHIP_ESP32C61: chip_report_printf("ESP32-C61\n"); break;
case CHIP_ESP32H21: chip_report_printf("ESP32-H21\n"); break;
#endif
default: chip_report_printf("Unknown %d\n", info.model); break;
}
printPkgVersion();
Expand Down
14 changes: 11 additions & 3 deletions cores/esp32/esp32-hal-cpu.c
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Expand Up @@ -19,7 +19,7 @@
#include "esp_attr.h"
#include "esp_log.h"
#include "soc/rtc.h"
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4)
#if !defined(CONFIG_IDF_TARGET_ESP32C2) && !defined(CONFIG_IDF_TARGET_ESP32C6) && !defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5)
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#endif
Expand Down Expand Up @@ -48,6 +48,8 @@
#include "esp32h2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C5
#include "esp32c5/rom/rtc.h"
#else
#error Target CONFIG_IDF_TARGET is not supported
#endif
Expand Down Expand Up @@ -179,7 +181,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
rtc_cpu_freq_config_t conf, cconf;
uint32_t capb, apb;
//Get XTAL Frequency and calculate min CPU MHz
#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))
#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5))
rtc_xtal_freq_t xtal = rtc_clk_xtal_freq_get();
#endif
#if CONFIG_IDF_TARGET_ESP32
Expand All @@ -195,7 +197,7 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
}
}
#endif
#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4))
#if (!defined(CONFIG_IDF_TARGET_ESP32H2) && !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5))
if (cpu_freq_mhz > xtal && cpu_freq_mhz != 240 && cpu_freq_mhz != 160 && cpu_freq_mhz != 120 && cpu_freq_mhz != 80) {
if (xtal >= RTC_XTAL_FREQ_40M) {
log_e("Bad frequency: %u MHz! Options are: 240, 160, 120, 80, %u, %u and %u MHz", cpu_freq_mhz, xtal, xtal / 2, xtal / 4);
Expand Down Expand Up @@ -265,6 +267,12 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
(conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M")),
conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
);
#elif defined(CONFIG_IDF_TARGET_ESP32C5)
log_d(
"%s: %u / %u = %u Mhz, APB: %u Hz",
(conf.source == SOC_CPU_CLK_SRC_PLL_F240M || conf.source == SOC_CPU_CLK_SRC_PLL_F160M) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M"),
conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
);
#else
log_d(
"%s: %u / %u = %u Mhz, APB: %u Hz", (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "17.5M"),
Expand Down
7 changes: 6 additions & 1 deletion cores/esp32/esp32-hal-i2c-slave.c
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Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,9 @@
#include "soc/i2c_struct.h"
#include "soc/periph_defs.h"
#include "hal/i2c_ll.h"
#ifndef CONFIG_IDF_TARGET_ESP32C5
#include "hal/clk_gate_ll.h"
#endif
#include "esp32-hal-log.h"
#include "esp32-hal-i2c-slave.h"
#include "esp32-hal-periman.h"
Expand Down Expand Up @@ -325,7 +327,7 @@ esp_err_t i2cSlaveInit(uint8_t num, int sda, int scl, uint16_t slaveID, uint32_t
frequency = 100000L;
}
frequency = (frequency * 5) / 4;
#if !defined(CONFIG_IDF_TARGET_ESP32P4)
#if !defined(CONFIG_IDF_TARGET_ESP32P4) && !defined(CONFIG_IDF_TARGET_ESP32C5)
if (i2c->num == 0) {
periph_ll_enable_clk_clear_rst(PERIPH_I2C0_MODULE);
#if SOC_HP_I2C_NUM > 1
Expand Down Expand Up @@ -556,6 +558,9 @@ static bool i2c_slave_set_frequency(i2c_slave_struct_t *i2c, uint32_t clk_speed)
i2c_ll_set_source_clk(i2c->dev, SOC_MOD_CLK_APB); /*!< I2C source clock from APB, 80M*/
}
#elif SOC_I2C_SUPPORT_XTAL
#ifndef XTAL_CLK_FREQ
#define XTAL_CLK_FREQ APB_CLK_FREQ
#endif
i2c_ll_master_cal_bus_clk(XTAL_CLK_FREQ, clk_speed, &clk_cal);
I2C_CLOCK_SRC_ATOMIC() {
i2c_ll_set_source_clk(i2c->dev, SOC_MOD_CLK_XTAL); /*!< I2C source clock from XTAL, 40M */
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