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litex: gen: fhdl: verilog.py: resolve slice in lower_complex_slices() #2165
litex: gen: fhdl: verilog.py: resolve slice in lower_complex_slices() #2165
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Thanks @maass-hamburg, can you verify that the following designs that were problematic with the previous changes are correctly building with the newer changes?:
and
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On Wed, Jan 22, 2025 at 01:24:06AM -0800, enjoy-digital wrote:
Thanks @maass-hamburg, can you verify that the following designs that were
problematic with the previous changes are correctly building with the newer
changes?:
python3 -m litex_boards.targets.lambdaconcept_ecpix5 --build --cpu-type rocket
--cpu-variant linux --cpu-num-cores 1 --cpu-mem-width 2 --sys-clk-freq 50e6
--with-ethernet --with-sdcard --yosys-flow3
and
python3 -m litex_boards.targets.digilent_nexys_video.py --build --cpu-type
rocket --cpu-variant linux --cpu-num-cores 4 --cpu-mem-width 2 --sys-clk-freq
50e6 --with-ethernet --with-sdcard --with-sata --sata-gen 1
So far, these seem to build fine for me. I have to leave and won't be
able to test whether the result actually *works* (to be 100% sure) for
another few hours, but the verilog parse error we encountered with the
earlier attempt is no longer happening.
Thanks
--Gabriel
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resove slices in lower_complex_slices() completly, to reduce complexity in the verilog files. Signed-off-by: Fin Maaß <[email protected]>
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I removed the change of |
On Wed, Jan 22, 2025 at 06:47:00AM -0800, Fin Maaß wrote:
I removed the change of _generate_slice, as I had already moved the slice
resolving logic to the lowerer and don't have to do that twice.
litex/rocket still builds (and works) correctly.
Thanks for updating the PR!
Cheers,
--Gabriel
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If the Slice is inside the boarders of one Objekt of Cat or Replicate resolve it too. Signed-off-by: Fin Maaß <[email protected]>
Thanks @maass-hamburg and @gsomlo for the feedback. This is merged. |
bring back lower_complex_slices() as it is sometimes needed.
for example, when a Slice of a Cat() is done.
migen: m-labs/migen#301