Allow longer time for low performance architectures#198
Open
U2FsdGVkX1 wants to merge 2 commits intoelastic:mainfrom
Open
Allow longer time for low performance architectures#198U2FsdGVkX1 wants to merge 2 commits intoelastic:mainfrom
U2FsdGVkX1 wants to merge 2 commits intoelastic:mainfrom
Conversation
|
💚 CLA has been signed |
Member
|
I'm slightly reluctant to make CI 3 seconds slower. However, I can't merge this until you have signed the CLA, sorry. |
Author
Oh I forgot about that. Sorry. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
I am a Fedora packager and recently observed that many tests were failing due to timeouts during the check stage. This issue is particularly noticeable on low-performance devices and current RISC-V hardware. The existing 2-second timeout is insufficient for these systems, leading to test failures.
To address this, I have adjusted the timeout duration from 2 seconds to 5 seconds. This change has been tested on the SG2042 (a RISC-V chip) and has shown to work well.