Silicon/Rockchip: DWC3: Disable SS instances in park mode

No, I did not notice any issues, but Rockchip have enabled this quirk in their kernel, so let's do the same. Apparently, on some implementations of DWC3 the controller would halt under high load and never come back online.
edk2-porting · Aug 30, 2023 · f187fa7 · f187fa7
1 parent dbaeeac
commit f187fa7
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diff --git a/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c b/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c
@@ -194,6 +194,8 @@ XhciCoreInit (
   MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_DEPOCHANGE, 0);
   /* snps,dis-tx-ipgap-linecheck-quirk */
   MmioOr32 ((UINTN)&Dwc3Reg->GUctl1, DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS);
+  /* snps,parkmode-disable-ss-quirk */
+  MmioOr32 ((UINTN)&Dwc3Reg->GUctl1, DWC3_GUCTL1_PARKMODE_DISABLE_SS);
 
   /* Set max speed */
   MmioAndThenOr32 ((UINTN)&Dwc3Reg->DCfg, ~DCFG_SPEED_MASK, DCFG_SPEED_SS);

diff --git a/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h b/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h
@@ -35,6 +35,7 @@
 
 /* Global UCTL1 Register */
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS     BIT28
+#define DWC3_GUCTL1_PARKMODE_DISABLE_SS        BIT17
 
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST            BIT31