Clean up one false failing test and prepare almost full/empty flags

.gitignore

@@ -1,2 +1,3 @@
 *.out
 *.vcd
+*.lxt

sim/test/async_fifo_unit_test.sv

@@ -15,11 +15,13 @@ module async_fifo_unit_test;
     reg              winc;
     reg  [DSIZE-1:0] wdata;
     wire             wfull;
+    wire             awfull;
     reg              rclk;
     reg              rrst_n;
     reg              rinc;
     wire [DSIZE-1:0] rdata;
     wire             rempty;
+    wire             arempty;
 
     async_fifo 
     #(
@@ -33,11 +35,13 @@ module async_fifo_unit_test;
     winc,
     wdata,
     wfull,
+    awfull,
     rclk,
     rrst_n,
     rinc,
     rdata,
-    rempty
+    rempty,
+    arempty
     );
 
     // An example to create a clock
@@ -47,10 +51,13 @@ module async_fifo_unit_test;
     always #3 rclk <= ~rclk;
 
     // An example to dump data for visualization
-    initial $dumpvars(0,async_fifo_unit_test);
+    initial begin
+        $dumpvars(0, async_fifo_unit_test);
+    end
 
     task setup();
     begin
+
         wrst_n = 1'b0;
         winc = 1'b0;
         wdata = 0;
@@ -61,6 +68,7 @@ module async_fifo_unit_test;
         rrst_n = 1;
         #200;
         @(posedge wclk);
+
     end
     endtask
 
@@ -74,75 +82,114 @@ module async_fifo_unit_test;
 
     `UNIT_TEST(IDLE)
 
-        `INFO("Start IDLE test");
+        `INFO("Test: IDLE");
         `FAIL_IF(wfull);
         `FAIL_IF(!rempty);
 
     `UNIT_TEST_END
 
     `UNIT_TEST(SIMPLE_WRITE_AND_READ)
 
-        `INFO("Simple write then read");
+        `INFO("Test: Simple write then read");
 
         @(posedge wclk)
+
         winc = 1;
         wdata = 32'hA;
+
         @(posedge wclk)
+
         winc = 0;
+
         @(posedge rclk)
-        wait (rempty == 0);
+
+        wait (rempty == 1'b0);
+
         `FAIL_IF_NOT_EQUAL(rdata, 32'hA);
 
     `UNIT_TEST_END
 
     `UNIT_TEST(MULTIPLE_WRITE_AND_READ)
 
-        `INFO("Multiple write then read");
+        `INFO("Test: Multiple write then read");
 
-        for (i=0; i<20; i = i+1) begin
-            @(posedge wclk)
+        for (i=0; i<10; i=i+1) begin
+            @(negedge wclk);
             winc = 1;
             wdata = i;
-            @(posedge wclk)
-            winc = 0;
-            @(posedge rclk)
-            wait (rempty == 0);
+            // $display("DEBUG:   [%g]: %x", $time, i);
+        end
+        @(negedge wclk);
+        winc = 0;
+
+        #100;
+
+        @(posedge rclk);
+
+        rinc = 1;
+        for (i=0; i<10; i=i+1) begin
+            @(posedge rclk);
             `FAIL_IF_NOT_EQUAL(rdata, i);
+            // $display("DEBUG:   [%g]: %x", $time, rdata);
         end
 
     `UNIT_TEST_END
 
     `UNIT_TEST(TEST_FULL_FLAG)
 
-        `INFO("Test full flag test");
+        `INFO("Test: full flag test");
 
-        for (i=0; i<2**ASIZE; i = i+1) begin
-            @(posedge wclk)
-            winc = 1;
+        winc = 1;
+
+        for (i=0; i<2**ASIZE; i=i+1) begin
+            @(negedge wclk)
             wdata = i;
         end
-        @(posedge wclk)
-        @(posedge wclk)
+
+        @(negedge wclk);
+        winc = 0;
+
         @(posedge wclk)
         `FAIL_IF_NOT_EQUAL(wfull, 1);
+
         #50;
 
     `UNIT_TEST_END
 
     `UNIT_TEST(TEST_EMPTY_FLAG)
 
-        `INFO("Test empty flag test");
+        `INFO("Test: empty flag test");
 
-        for (i=0; i<2**ASIZE; i = i+1) begin
+        for (i=0; i<2**ASIZE; i=i+1) begin
             @(posedge wclk)
             winc = 1;
             wdata = i;
         end
-        `FAIL_IF_NOT_EQUAL(rempty, 1);
+        `FAIL_IF_NOT_EQUAL(rempty, 0);
         #50;
 
     `UNIT_TEST_END
 
+    `UNIT_TEST(TEST_SIMPLE_ALMOST_FULL_FLAG)
+
+        `INFO("Test: Almost full flag simple test");
+
+        winc = 1;
+        for (i=0; i<2**ASIZE; i=i+1) begin
+            @(negedge wclk)
+            wdata = i;
+        end
+
+        @(negedge wclk);
+        winc = 0;
+
+        @(posedge wclk)
+        `FAIL_IF_NOT_EQUAL(wfull, 1);
+
+        #50;
+
+    `UNIT_TEST_END
+
     `UNIT_TESTS_END
 
 endmodule

sim/test/wave.gtkw

@@ -1,42 +1,96 @@
 [*]
-[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Fri Sep  1 12:55:43 2017
+[*] GTKWave Analyzer v3.3.85 (w)1999-2017 BSI
+[*] Wed Oct  4 21:08:19 2017
 [*]
-[dumpfile] "/home/damien/workspace/async_fifo/sim/test/dump.lxt"
-[dumpfile_mtime] "Fri Sep  1 12:55:22 2017"
-[dumpfile_size] 3913
-[savefile] "/home/damien/workspace/async_fifo/sim/test/wave.gtkw"
-[timestart] 0
-[size] 1000 600
-[pos] -1 -1
-*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[dumpfile] "/Users/damien/dev/verilog/async_fifo/sim/test/dump.lxt"
+[dumpfile_mtime] "Wed Oct  4 20:53:16 2017"
+[dumpfile_size] 3687
+[savefile] "/Users/damien/dev/verilog/async_fifo/sim/test/wave.gtkw"
+[timestart] 1089250
+[size] 1920 1056
+[pos] -1 0
+*-13.241215 1077000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] async_fifo_unit_test.
+[treeopen] async_fifo_unit_test.dut.
 [sst_width] 196
-[signals_width] 238
+[signals_width] 332
 [sst_expanded] 1
-[sst_vpaned_height] 150
+[sst_vpaned_height] 575
+@200
+-TB
 @22
+async_fifo_unit_test.svut_error[31:0]
+async_fifo_unit_test.svut_nb_test[31:0]
+async_fifo_unit_test.svut_nb_test_success[31:0]
 async_fifo_unit_test.i[31:0]
 @28
+async_fifo_unit_test.wclk[0]
+async_fifo_unit_test.wrst_n[0]
+async_fifo_unit_test.winc[0]
+@22
+async_fifo_unit_test.wdata[31:0]
+@28
+async_fifo_unit_test.wfull[0]
 async_fifo_unit_test.rclk[0]
+async_fifo_unit_test.rrst_n[0]
+async_fifo_unit_test.rinc[0]
 @22
 async_fifo_unit_test.rdata[31:0]
 @28
 async_fifo_unit_test.rempty[0]
-async_fifo_unit_test.rinc[0]
-async_fifo_unit_test.rrst_n[0]
+@200
+-DUT
+@28
+async_fifo_unit_test.dut.rclk[0]
+async_fifo_unit_test.dut.rrst_n[0]
+async_fifo_unit_test.dut.rinc[0]
 @22
-async_fifo_unit_test.svut_error[31:0]
-async_fifo_unit_test.svut_nb_test[31:0]
-async_fifo_unit_test.svut_nb_test_success[31:0]
-async_fifo_unit_test.svut_timeout[31:0]
-async_fifo_unit_test.svut_timeout_max[31:0]
+async_fifo_unit_test.dut.raddr[3:0]
+async_fifo_unit_test.dut.rdata[31:0]
 @28
-async_fifo_unit_test.wclk[0]
+async_fifo_unit_test.dut.rempty[0]
 @22
-async_fifo_unit_test.wdata[31:0]
+async_fifo_unit_test.dut.rptr[4:0]
+async_fifo_unit_test.dut.rq2_wptr[4:0]
 @28
-async_fifo_unit_test.wfull[0]
-async_fifo_unit_test.winc[0]
-async_fifo_unit_test.wrst_n[0]
+async_fifo_unit_test.dut.wclk[0]
+async_fifo_unit_test.dut.wrst_n[0]
+async_fifo_unit_test.dut.winc[0]
+async_fifo_unit_test.dut.wfull[0]
+@22
+async_fifo_unit_test.dut.wdata[31:0]
+async_fifo_unit_test.dut.wptr[4:0]
+async_fifo_unit_test.dut.wq2_rptr[4:0]
+@200
+-FIFO MEM
+@28
+async_fifo_unit_test.dut.fifomem.wclk[0]
+async_fifo_unit_test.dut.fifomem.wclken[0]
+@22
+async_fifo_unit_test.dut.fifomem.waddr[3:0]
+async_fifo_unit_test.dut.fifomem.wdata[31:0]
+@28
+async_fifo_unit_test.dut.fifomem.wfull[0]
+@22
+async_fifo_unit_test.dut.fifomem.raddr[3:0]
+async_fifo_unit_test.dut.fifomem.rdata[31:0]
+@200
+-RD PTR EMPTY
+@28
+async_fifo_unit_test.dut.rptr_empty.rclk[0]
+async_fifo_unit_test.dut.rptr_empty.rrst_n[0]
+async_fifo_unit_test.dut.rptr_empty.rinc[0]
+async_fifo_unit_test.dut.rptr_empty.rempty[0]
+@22
+async_fifo_unit_test.dut.rptr_empty.raddr[3:0]
+async_fifo_unit_test.dut.rptr_empty.rbin[4:0]
+async_fifo_unit_test.dut.rptr_empty.rbinnext[4:0]
+@28
+async_fifo_unit_test.dut.rptr_empty.rempty_val[0]
+@22
+async_fifo_unit_test.dut.rptr_empty.rgraynext[4:0]
+async_fifo_unit_test.dut.rptr_empty.rptr[4:0]
+@23
+async_fifo_unit_test.dut.rptr_empty.rq2_wptr[4:0]
 [pattern_trace] 1
 [pattern_trace] 0