update dependencies

mm0-rs/Cargo.toml

@@ -50,7 +50,7 @@ annotate-snippets = "0.11"
 libc = "0.2"
 zerocopy = "0.7"
 memchr = "2.7"
-bit-set = "0.6"
+bit-set = "0.8"
 typed-arena = "2.0"
 mm0_deepsize_derive = { path = "components/mm0_deepsize_derive", optional = true }
 debug_derive = { path = "components/debug_derive" }

mm0-rs/components/mm0_deepsize/Cargo.toml

@@ -18,8 +18,8 @@ mm0_deepsize_derive = { version = "0.1.1", path = "../mm0_deepsize_derive" }
 num = { version = "0.4", optional = true }
 typed-arena = { version = "2.0", optional = true }
 smallvec = { version = "1.8", optional = true }
-bit-vec = { version = "0.7", optional = true }
-bit-set = { version = "0.6", optional = true }
+bit-vec = { version = "0.8", optional = true }
+bit-set = { version = "0.8", optional = true }
 lsp-types = { version = "0.97", optional = true }
 futures = { version = "0.3", optional = true }
 hybrid-rc = { version = "0.6", optional = true }

mm0-rs/components/mmcc/Cargo.toml

@@ -23,13 +23,13 @@ if_chain = "1.0"
 smallvec = { version = "1.8", features = ["union"] }
 arrayvec = "0.7"
 im = "15.1"
-bit-vec = "0.7"
-bit-set = "0.6"
+bit-vec = "0.8"
+bit-set = "0.8"
 hashbrown = "0.14"
 typed-arena = "2.0"
 # simplelog = "0.11"
 bumpalo = { version = "3.10", features = ["boxed", "collections"] }
-regalloc2 = "0.2"
+regalloc2 = "0.9"
 mm0_util = { path = "../mm0_util", default-features = false }
 mm0_deepsize = { path = "../mm0_deepsize", optional = true, features = [
   "num", "typed-arena", "smallvec", "bit-vec", "bit-set"] }

mm0-rs/components/mmcc/src/arch/x86/mod.rs

@@ -85,17 +85,51 @@ pub(crate) fn caller_saved() -> impl DoubleEndedIterator<Item=PReg> + Clone {
 }
 
 pub(crate) static MACHINE_ENV: Lazy<MachineEnv> = Lazy::new(|| MachineEnv {
-  preferred_regs_by_class: [CALLER_SAVED.map(|r| r.0).into(), vec![]],
-  non_preferred_regs_by_class: [CALLEE_SAVED.map(|r| r.0).into(), vec![]],
+  preferred_regs_by_class: [CALLER_SAVED.map(|r| r.0).into(), vec![], vec![]],
+  non_preferred_regs_by_class: [CALLEE_SAVED.map(|r| r.0).into(), vec![], vec![]],
+  scratch_by_class: [None; 3],
   fixed_stack_slots: vec![],
 });
 
-#[derive(Copy, Clone, Default)]
-pub(crate) struct PRegSet(u16);
+/// A set of physical registers. For x86, this can be stored as a 16 bit bitfield.
+#[derive(Copy, Clone, Default, Debug)]
+pub struct PRegSet(u16);
 impl PRegSet {
   #[inline] pub(crate) fn insert(&mut self, r: PReg) { self.0 |= 1 << r.index() }
   #[inline] pub(crate) fn get(self, r: PReg) -> bool { self.0 & (1 << r.index()) != 0 }
   #[inline] pub(crate) fn remove(&mut self, r: PReg) { self.0 &= !(1 << r.index()) }
+
+  /// An iterator over the registers in the set.
+  pub fn iter(self) -> impl Iterator<Item=PReg> {
+    (0..16).map(PReg::new).filter(move |&r| self.get(r))
+  }
+}
+
+impl std::ops::BitOrAssign for PRegSet {
+  fn bitor_assign(&mut self, rhs: Self) {
+    self.0 |= rhs.0
+  }
+}
+
+impl From<PRegSet> for regalloc2::PRegSet {
+  fn from(val: PRegSet) -> Self {
+    let mut out = Self::empty();
+    for i in 0..16 {
+      let r = PReg::new(i);
+      if val.get(r) {
+        out.add(r.0)
+      }
+    }
+    out
+  }
+}
+
+impl FromIterator<PReg> for PRegSet {
+  fn from_iter<T: IntoIterator<Item = PReg>>(iter: T) -> Self {
+    let mut out = Self::default();
+    for i in iter { out.insert(i); }
+    out
+  }
 }
 
 /// These indicate the form of a scalar shift/rotate: left, signed right, unsigned right.
@@ -937,7 +971,7 @@ pub(crate) enum Inst {
     f: ProcId,
     operands: Box<[Operand]>,
     /// If `clobbers = None` then this call does not return.
-    clobbers: Option<Box<[PReg]>>,
+    clobbers: Option<PRegSet>,
   },
   // /// Indirect call: `callq r/m`.
   // CallUnknown {
@@ -981,7 +1015,6 @@ impl Debug for Inst {
         let vreg = VReg(self.0.vreg());
         match self.0.kind() {
           OperandKind::Def => write!(f, "out ")?,
-          OperandKind::Mod => write!(f, "inout ")?,
           OperandKind::Use => {}
         }
         match self.0.constraint() {
@@ -1146,11 +1179,11 @@ impl VInst for Inst {
     }
   }
 
-  fn clobbers(&self) -> &[PReg] {
+  fn clobbers(&self) -> PRegSet {
     match self {
-      Inst::CallKnown { clobbers: Some(cl), .. } => cl,
-      Inst::SysCall { f, .. } if f.returns() => &[RCX, R11],
-      _ => &[],
+      &Inst::CallKnown { clobbers: Some(cl), .. } => cl,
+      Inst::SysCall { f, .. } if f.returns() => [RCX, R11].into_iter().collect(),
+      _ => Default::default(),
     }
   }
 }

mm0-rs/components/mmcc/src/build_vcode.rs

@@ -787,7 +787,7 @@ impl<'a> LowerCtx<'a> {
       self.emit(Inst::CallKnown {
         f,
         operands: operands.into(),
-        clobbers: Some(fabi.clobbers.clone()),
+        clobbers: Some(fabi.clobbers),
       });
       let mut ret_regs = ret_regs.into_iter();
       for (arg, &(vr, v)) in fabi.rets.iter().zip(rets) {

mm0-rs/components/mmcc/src/regalloc.rs

@@ -23,7 +23,7 @@ use crate::types::vcode::{self, IsReg, InstId, ProcAbi, SpillId, BlockId, ChunkV
 
 impl<I: vcode::Inst> vcode::VCode<I> {
   fn do_regalloc(&self) -> regalloc2::Output {
-    let opts = regalloc2::RegallocOptions { verbose_log: true };
+    let opts = regalloc2::RegallocOptions { verbose_log: true, validate_ssa: true };
     regalloc2::run(self, &MACHINE_ENV, &opts).expect("fatal regalloc error")
   }
 }
@@ -283,7 +283,8 @@ fn get_clobbers(vcode: &VCode, out: &regalloc2::Output) -> PRegSet {
     if let Some(r) = to.as_reg() { result.insert(PReg(r)) }
   }
   for (i, _) in vcode.insts.enum_iter() {
-    for &r in vcode.inst_clobbers(i) { result.insert(PReg(r)) }
+    use crate::types::vcode::Inst;
+    result |= vcode.insts[i].clobbers();
     for (op, alloc) in vcode.inst_operands(i).iter().zip(out.inst_allocs(i)) {
       if op.kind() != regalloc2::OperandKind::Use {
         if let Some(r) = alloc.as_reg() { result.insert(PReg(r)) }

mm0-rs/components/mmcc/src/types/vcode.rs

@@ -2,7 +2,7 @@
 
 use std::{collections::HashMap, fmt::{Debug, Display}, iter::FromIterator};
 
-use crate::{Idx, types::{IdxVec, mir}, arch::PReg};
+use crate::{arch::{PReg, PRegSet}, types::{mir, IdxVec}, Idx};
 
 use mm0_util::u32_as_usize;
 pub(crate) use regalloc2::{RegClass, InstRange, Operand, Inst as InstId};
@@ -112,7 +112,7 @@ pub trait Inst: Sized {
   fn collect_operands(&self, _: &mut Vec<Operand>);
 
   /// Get the clobbers for an instruction.
-  fn clobbers(&self) -> &[PReg];
+  fn clobbers(&self) -> PRegSet;
 }
 
 /// Conceptually the same as `IdxVec<I, Vec<T>>`, but shares allocations between the vectors.
@@ -249,7 +249,7 @@ pub struct ProcAbi {
   /// The total size of the stack-allocated incoming arguments in bytes
   pub args_space: u32,
   /// The registers that are clobbered by the call.
-  pub clobbers: Box<[PReg]>,
+  pub clobbers: PRegSet,
 }
 
 /// A low level representation of a function, after instruction selection but before
@@ -375,13 +375,10 @@ impl<I: Inst> regalloc2::Function for VCode<I> {
     self.insts[insn].branch_blockparams(succ_idx)
   }
 
-  fn is_move(&self, insn: InstId) -> Option<(Operand, Operand)> { self.insts[insn].is_move() }
+  // fn is_move(&self, insn: InstId) -> Option<(Operand, Operand)> { self.insts[insn].is_move() }
   fn inst_operands(&self, insn: InstId) -> &[Operand] { &self.operands[insn] }
-  fn inst_clobbers(&self, insn: InstId) -> &[regalloc2::PReg] {
-    let ret = self.insts[insn].clobbers();
-    #[allow(clippy::transmute_ptr_to_ptr)]
-    // Safety: `PReg` is repr(transparent)
-    unsafe { std::mem::transmute::<&[PReg], &[regalloc2::PReg]>(ret) }
+  fn inst_clobbers(&self, insn: InstId) -> regalloc2::PRegSet {
+    self.insts[insn].clobbers().into()
   }
   fn num_vregs(&self) -> usize { self.num_vregs }
   fn spillslot_size(&self, _: regalloc2::RegClass) -> usize { 1 }

mm0-rs/src/mmc/proof/compiler.rs

@@ -1225,7 +1225,7 @@ impl<'a> ProcProver<'a> {
       let (vctx1, sz1) = (vctx.e, *vctx.nvars);
       let mctx1 = mctx.1;
       let args2 = app!(self.thm, (mkArgs args mctx1));
-      let (clob, h3) = self.accum_clob(&mut mctx, abi.clobbers.iter().map(|r| r.index()));
+      let (clob, h3) = self.accum_clob(&mut mctx, abi.clobbers.iter().map(PReg::index));
       let mctx2 = mctx.1;
       let h4 = self.ok_prologue(&mut mctx, prol);
       let mctx3 = mctx.1;