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Pull requests list

SVA: sequence repetition for proper sequences Verilog
#944 opened Jan 21, 2025 by kroening Loading…
SVA sequence and/or Verilog
#943 opened Jan 20, 2025 by kroening Loading…
Add chipsalliance/sv-tests to CI
#939 opened Jan 17, 2025 by kroening • Draft
aval/bval lowering for reduction operators Verilog
#930 opened Jan 16, 2025 by kroening • Draft
vlindex: fix parsing for constraint_block
#924 opened Jan 6, 2025 by kroening • Draft
SystemVerilog: fix identifier on enum type Verilog
#919 opened Jan 2, 2025 by kroening • Draft
bump CBMC dependency
#916 opened Jan 2, 2025 by kroening • Draft
liveness engine engines
#915 opened Dec 29, 2024 by kroening • Draft
SMV: clean up parse tree SMV
#909 opened Dec 27, 2024 by kroening • Draft
SMV: typechecking for ?: SMV
#906 opened Dec 26, 2024 by kroening • Draft
SMV: typechecking for unary minus SMV
#893 opened Dec 20, 2024 by kroening • Draft
SystemVerilog: type parameter ports Verilog
#842 opened Nov 21, 2024 by kroening • Draft
SVA/LTL property instrumentation engines
#797 opened Nov 3, 2024 by kroening • Draft
Verilog: use zero_extend_exprt Verilog
#796 opened Nov 1, 2024 by kroening • Draft
word-level BMC: add missing SVA expressions Verilog
#759 opened Oct 9, 2024 by kroening • Draft
Verilog: default aval/bval lowering Verilog
#668 opened Sep 5, 2024 by kroening • Draft
Verilog: expr2verilog can now decode aval/bval constants Verilog
#570 opened Jun 22, 2024 by kroening • Draft
SAT-based neural ranking engine engines
#524 opened May 27, 2024 by kroening Loading…
SystemVerilog: implement package import Verilog
#483 opened May 5, 2024 by kroening • Draft
Verilog: fix for indexed part select Verilog
#424 opened Mar 21, 2024 by kroening • Draft
ebmc: HWMCC 2017 benchmarks in CI
#387 opened Feb 29, 2024 by kroening Loading…
2
add AIGER frontend
#383 opened Feb 28, 2024 by kroening • Draft
netlistt: remove dependency on var_mapt
#382 opened Feb 28, 2024 by kroening • Draft
nuterm using libtorch engines
#328 opened Jan 3, 2024 by kroening Loading…
@tautschnig
Verilog: add symbols below generate-if Verilog
#318 opened Dec 24, 2023 by kroening • Draft
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