My #1 documentation for my experimental FreeBot code and documentation

micro-ROS Zephyr module and sample code

LLEF is a plugin for LLDB to make it more useful for RE and VR

GEF (GDB Enhanced Features) - a modern experience for GDB with advanced debugging capabilities for exploit devs & reverse engineers on Linux

LVGL bindings for Rust. A powerful and easy-to-use embedded GUI with many widgets, advanced visual effects (opacity, antialiasing, animations) and low memory requirements (16K RAM, 64K Flash).

SERV - The SErial RISC-V CPU

This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate …

Bao, a Lightweight Static Partitioning Hypervisor

Standalone drivers for peripherals present in Nordic SoCs

This tool lets you search your gadgets on your binaries to facilitate your ROP exploitation. ROPgadget supports ELF, PE and Mach-O format on x86, x64, ARM, ARM64, PowerPC, SPARC, MIPS, RISC-V 64, a…

The fuzzer afl++ is afl with community patches, qemu 5.1 upgrade, collision-free coverage, enhanced laf-intel & redqueen, AFLfast++ power schedules, MOpt mutators, unicorn_mode, and a lot more!

BINSEC binary-level open-source platform

symbolic execution engine for Rust

A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one

cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.

🔍 A Hex Editor for Reverse Engineers, Programmers and people who value their retinas when working at 3 AM.

FreeRTOS kernel files only, submoduled into https://github.com/FreeRTOS/FreeRTOS and various other repos.

'Classic' FreeRTOS distribution. Started as Git clone of FreeRTOS SourceForge SVN repo. Submodules the kernel.

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

RISC-V HS-mode hypervisor extension tests

A project for generating C bindings from Rust code

Sail code model of the CHERIoT ISA

Coffer is a RISC-V trusted execution environment developed in Rust.

Mirror of the Xen Repository (PRs not accepted see: http://wiki.xenproject.org/wiki/Submitting_Xen_Project_Patches)

Sail Asciidoctor plugin

RISC-V Open Source Supervisor Binary Interface

Xvisor: eXtensible Versatile hypervISOR

hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V