Expose debug ports as a RISC-V Debug Module

[steven-bellock]

Previous issues:

• Caliptra: JTAG IDCODE register reports manufacturer is Western Digital #289
• VeeR: Remove (or make optional) the JTAG IDCODE command Cores-VeeR-EL2#146
• RISC-V Debug: Clarify JTAG IDCODE requirement in an SOC riscv/riscv-debug-spec#924

To debug the firmware on Caliptra's RISC-V processor caliptra_top requires

caliptra-rtl/src/integration/rtl/caliptra_top.sv

Lines 39 to 44 in 9e7f7f2

	//JTAG Interface
	input logic jtag_tck, // JTAG clk
	input logic jtag_tms, // JTAG TMS
	input logic jtag_tdi, // JTAG tdi
	input logic jtag_trst_n, // JTAG Reset
	output logic jtag_tdo, // JTAG TDO

and a TAP controller is instantiated within Caliptra. Most (all?) Integrators of Caliptra will already have a top-level TAP controller and so Caliptra's instantiation of one is excessive and unneeded. In particular caliptra_top should be treated as a RISC-V Debug Module and expose the RISC-V DMI ports

caliptra-rtl/src/riscv_core/veer_el2/rtl/el2_veer.sv

Lines 374 to 378 in 9e7f7f2

	input logic dmi_reg_en, // read or write
	input logic [6:0] dmi_reg_addr, // address of DM register
	input logic dmi_reg_wr_en, // write instruction
	input logic [31:0] dmi_reg_wdata, // write data
	output logic [31:0] dmi_reg_rdata,

[calebofearth]

Clarification question:
This feature needs to be implemented by the VeeR team since there is no current mechanism to export just the DMI ports from EL2 VeeR core.
Do you propose waiting until we can discuss this feature within the Caliptra community and reach consensus before filing this request to the VeeR team?

[steven-bellock]

Caliptra can either

1. Instantiate el2_veer instead of el2_veer_wrapper OR
2. Request an option that the DMI ports be exposed in el2_veer_wrapper instead of the TAP ports as well as removing the TAP controller entirely from el2_veer_wrapper.

But in either case this entire issue should be discussed and approved broadly before implementing.

[bharatpillilli]

Resolved with this? =-> #415

@steven-bellock ?

[steven-bellock]

Resolved with this? =-> #415

No, this is more far-reaching. For security, most folks will just tie Caliptra's JTAG inputs to 0. If Caliptra is being integrated into an SOC and they want the ability to debug the microcontroller, then this enhancement is desirable since it's a cleaner solution. Would like to hear @nstewart-amd's thoughts as well.

[bharatpillilli]

You can control microcontroller by sending JTAG commands - and the command can be mastered to CLTAP at SoC level. This jtag can be treated as slave TAP controller or a TAP EP under the control of CLTAP. What are we missing?

[bharatpillilli]

Spoke to few other indusrty experts and my statements match to what other uCs do and how other IPs integrate in their environment on the TAP chain. Closing the issue.