Surelog sometimes discards last range select after access to struct member

[Szelwiga]

Surelog sometimes discards last range select after access to struct member

SystemVerilog code (a1.sv):

typedef struct packed {
    logic [1:0][3:0] a;
} tier1;

module top();
    tier1 xx;
    assign xx.a[1][3:2] = 2;
    assign xx.a[1][1:0] = 3;
endmodule

parsed with: surelog -parse -elabuhdm a1.sv produces UHDM Tree which doesn't contain [3:2]
and [1:0] range selects. This is easily visible, because SystemVerilog code (a2.sv):

typedef struct packed {
    logic [1:0][3:0] a;
} tier1;

module top();
    tier1 xx;
    assign xx.a[1] = 2;
    assign xx.a[1] = 3;
endmodule

produces identical UHDM Tree (with accuracy to debug information). Here is UHDM Tree fragment that is responsible for one of those assignments:

  |vpiContAssign:
  \_cont_assign: , line:7:12, endln:7:28
    |vpiParent:
    \_module_inst: work@top (work@top), file:a1.sv, line:5:1, endln:9:10
    |vpiRhs:
    \_constant: , line:7:27, endln:7:28
    |vpiLhs:
    \_hier_path: (xx.a[1]), line:7:12, endln:7:24
      |vpiParent:
      \_cont_assign: , line:7:12, endln:7:28
      |vpiActual:
      \_ref_obj: (xx), line:7:15, endln:7:16
        |vpiParent:
        \_hier_path: (xx.a[1]), line:7:12, endln:7:24
        |vpiName:xx
      |vpiActual:
      \_bit_select: ([email protected][1].a), line:7:17, endln:7:18
        |vpiParent:
        \_hier_path: (xx.a[1]), line:7:12, endln:7:24
        |vpiName:a
        |vpiFullName:[email protected][1].a
        |vpiIndex:
        \_constant: , line:7:17, endln:7:18
          |vpiParent:
          \_bit_select: ([email protected][1].a), line:7:17, endln:7:18
          |vpiDecompile:1
          |vpiSize:64
          |UINT:1
          |vpiConstType:9
      |vpiName:xx.a[1]

This example is trimmed down version of code from OpenTitan.