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Placement error #4
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Hi, |
I have added "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck]" to the file and build it well. But the DBG IP did not work well when I tried to connect the device. |
Hi @zhuzhizhan, to my knowledge, this Cores-SweRV_fpga repo hasn't been well maintained recently. Please look at https://github.com/chipsalliance/Cores-SweRVolf for a well-maintained alternative. Jan |
The design does not synthesize.
Version of the FPGA repository:
3b67dc9441f44708b7800ae90c7ef0149e295f72
Version of the swerv_eh1 repository:
48f01f101eeeb8c75013afb4546e01b0fda08984
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