only test_address_translation.py left

mtkcpu/cpu/cpu.py

@@ -150,6 +150,7 @@ def __init__(
 
         self.running_state = CpuRunningState()
         self.running_state_interface = CpuRunningStateExternalInterface()
+        self.running_state_interface._MustUse__used = True
 
 
     def elaborate(self, platform):

mtkcpu/tests/test_address_translation.py

@@ -5,7 +5,7 @@
 from mtkcpu.utils.tests.utils import (MemTestCase, MemTestSourceType, mem_test)
 
 from mtkcpu.cpu.priv_isa import PrivModeBits, pte_layout, satp_layout
-from mtkcpu.units.csr import RegisterResetValue
+from mtkcpu.units.csr.csr import RegisterResetValue
 
 # page tables phys. addresses must be aligned to 4K == 0x1000 bytes
 root_pt_offset = 0x2000

mtkcpu/tests/test_debug_unit.py

@@ -1,5 +1,6 @@
 #!/usr/bin/env python3
 
+from typing import Sequence
 from dataclasses import dataclass
 
 from amaranth.sim import Simulator, Settle
@@ -15,7 +16,7 @@
 from mtkcpu.units.debug.dmi_handlers import DMI_HANDLERS_MAP
 from mtkcpu.units.debug.impl_config import PROGBUFSIZE, PROGBUF_MMIO_ADDR
 from mtkcpu.units.debug.impl_config import DATASIZE
-from mtkcpu.units.csr_handlers import DCSR
+from mtkcpu.units.csr.csr_handlers import DCSR
 
 logging = get_color_logging_object()
 
@@ -526,7 +527,7 @@ def main_process():
         new_pc = pc // 2 + 0x1000
         assert new_pc != pc
 
-        yield dmi_monitor.cpu.csr_unit.reg_by_addr(CSRIndex.DPC).rec.r.eq(new_pc)
+        yield dmi_monitor.cpu.csr_unit.dpc.eq(new_pc)
 
         yield from DMCONTROL_setup_basic_fields(dmi_monitor=dmi_monitor, dmi_op=DMIOp.WRITE)
         yield dmi_monitor.cur_DMCONTROL.haltreq.eq(0)
@@ -656,7 +657,7 @@ def mepc():
         yield Passive()
         while True:
             pc = yield cpu.pc
-            mepc = yield cpu.csr_unit.mepc.value
+            mepc = yield cpu.csr_unit.mepc.as_value()
             instr = yield cpu.instr
             print("mepc", hex(mepc), "pc", hex(pc), "instr", hex(instr))
             yield
@@ -687,7 +688,7 @@ def main_process():
         yield from few_ticks()
 
         # TODO: hardcoded 'cause' field offset.
-        expected_dcsr_reset_value = DCSR()._reset_value.value | (DCSR_DM_Entry_Cause.HALTREQ << 6)
+        expected_dcsr_reset_value = DCSR.const() | (DCSR_DM_Entry_Cause.HALTREQ << 6)
 
         DCSR_ins = instructions.RiscvCsrRegister("dcsr", num=0x7b0)
 

mtkcpu/units/csr/csr.py

@@ -74,8 +74,11 @@ def __init__(self,
         self.rd_val = Signal(32)
         self.vld = Signal()
         self.illegal_insn = Signal()
-        # raise ValueError((hex(MISA.const().value)))
-        self.csr_regs = [x(my_reg_latch=Signal(32, reset=x.const().value)) for x in __class__.enabled_csr_regs(with_virtual_memory=with_virtual_memory)]
+        self.csr_regs = [
+            reg_constructor(my_reg_latch=Signal(32, reset=reg_constructor.const()))
+            for reg_constructor in
+            __class__.enabled_csr_regs(with_virtual_memory=with_virtual_memory)
+        ]
 
     def elaborate(self, platform):
         m = self.m = Module()

mtkcpu/units/csr/csr_handlers.py

@@ -42,7 +42,7 @@ def latch_whole_value_with_no_side_effect(self):
 
     @classmethod
     def const(cls) -> int:
-        return cls.layout.const(cls.reset())
+        return cls.layout.const(cls.reset()).value
 
     @staticmethod
     def reset() -> dict[str, int]:

mtkcpu/units/debug/dmi_handlers.py

@@ -223,7 +223,7 @@ def elaborate(self, _):
                             from mtkcpu.cpu.priv_isa import CSRIndex
                             cpu : MtkCpu = self.debug_unit.cpu
                             real_dpc = Signal(32)
-                            dpc = cpu.csr_unit.reg_by_addr(CSRIndex.DPC).rec.r
+                            dpc = cpu.csr_unit.dpc
                             with m.FSM():
                                 with m.State("SANITY_CHECK"):
                                     with m.If(~self.debug_unit.cpu.running_state.halted):

mtkcpu/utils/tests/dmi_utils.py

@@ -9,6 +9,8 @@
 from mtkcpu.cpu.cpu import MtkCpu
 from mtkcpu.units.debug.types import DMI_reg_kinds
 from mtkcpu.utils.tests.sim_tests import get_state_name
+from mtkcpu.cpu.isa import Funct3
+from mtkcpu.units.csr.csr_handlers import DCSR, DPC
 
 logging = get_color_logging_object()
 
@@ -573,10 +575,9 @@ def aux():
     return aux
 
 def monitor_writes_to_dcsr(dmi_monitor: DMI_Monitor):
-    from mtkcpu.cpu.isa import Funct3
-    from mtkcpu.units.csr_handlers import DCSR, DPC
-    dcsr_addr = DCSR().csr_idx
-    dpc_addr = DPC().csr_idx
+
+    dcsr_addr = DCSR().addr
+    dpc_addr = DPC().addr
 
     def aux():
         yield Passive()