feat(tricore): Initial tricore support #242

miguelafsilva5 · 2025-08-29T14:03:37Z

PR Description

This PR introduces the initial support for Infineon Tricore architectures.
This PR requires #218 to support boot from flash with a non-unified memory model.
The current state of this port supports baremetal and freeRTOS guests in single or multicore setups. At the moment, each guest is given an unique ID, and each core only executes one guest.

The following list shows what is missing:

DMA virtualization/isolation
History re-write and commit clean up
CI integration
bao-demos integration

DavidMCerdeira

This is just a quick review.
For now the my main comments are regarding stale code comments and magic numbers, I don't think my comments address them all, please check them more carefully than I did.
There's also some instances of using platformed defined values that need to be made more general to handle multiple platforms.

DavidMCerdeira · 2025-12-16T14:06:31Z

src/arch/tricore/inc/arch/cache.h

+
+#include <bao.h>
+
+#define CACHE_MAX_LVL 8 // Does this make sense in all architectures?


Do we need this?

DavidMCerdeira · 2025-12-16T14:07:13Z

src/arch/tricore/inc/arch/fences.h

+{
+    __asm__ volatile("isync\n\t" ::: "memory");
+}
+
+static inline void fence_ord_read(void)
+{
+    __asm__ volatile("isync\n\t" ::: "memory");
+}
+
+static inline void fence_ord(void)
+{
+    __asm__ volatile("isync\n\t" ::: "memory");
+}
+
+static inline void fence_sync_write(void)
+{
+    __asm__ volatile("isync\n\t" ::: "memory");
+}
+
+static inline void fence_sync_read(void)
+{
+    __asm__ volatile("isync\n\t" ::: "memory");
+}
+
+static inline void fence_sync(void)
+{
+    __asm__ volatile("isync\n\t" ::: "memory");
+}


Implement the correct fence

DavidMCerdeira · 2025-12-16T14:07:23Z

src/arch/tricore/inc/arch/hypercall.h

+#define HYPCALL_IN_ARG_REG(ARG)  ((ARG) + 1 + 15 + 5)
+#define HYPCALL_OUT_ARG_REG(ARG) (HYPCALL_IN_ARG_REG(ARG))
+
+// #define HYPCALL_ARG_REG(ARG) ((ARG) + REG_A0)


remove comment

DavidMCerdeira · 2025-12-16T14:07:38Z

src/arch/tricore/inc/arch/interrupts.h

+#define IPI_CPU_MSG            (0x1460 / 4) /* TODO this is the first GPSR in TC49 */
+#define GSPR_SRC_BASE          (0x1460 / 4) /* TODO this is the first GPSR in TC49 */


Move to a platform defined

DavidMCerdeira · 2025-12-16T14:08:32Z

src/arch/tricore/inc/arch/ir.h

+#define GET_IR_SR_VALID(reg)   (((reg) & IR_SR_VALID_MASK) >> IR_SR_VALID_POS)
+#define GET_IR_SR_PN(reg)      (((reg) & IR_SR_PN_MASK) >> IR_SR_PN_POS)
+
+/* ACCESSEN Register */


lost comment

DavidMCerdeira · 2025-12-16T14:22:05Z

src/arch/tricore/vm.c

+    // TODO: All vms start running at "same" time?
+    if (1) {
+        vcpu_arch_entry();
+    } /*else {
+        cpu_idle();
+    }*/


DavidMCerdeira · 2025-12-16T14:23:07Z

src/platform/drivers/tricore_uart/tricore_uart.c

+    uart->FLAGSENABLE = 0;
+    uart->FLAGSCLEAR = 0xFFFFFFFF;
+
+    uart->FLAGSENABLE = 1 << 16 | 1 << 18 | 1 << 26 | 1 << 27 | 1 << 30; // parity error PEE, frame


use macros instead of magic numbers

DavidMCerdeira · 2025-12-16T14:23:26Z

src/platform/tc4dx/platform.mk

+platform_description:=tc4dx_desc.c
+
+TRICORE_MCPU=tc4DAx
+#TRICORE_MCPU=tc4xx


DavidMCerdeira · 2025-12-16T14:23:55Z

Makefile

+		-Wstrict-prototypes -Wunused-but-set-variable \
+		-Wno-multistatement-macros


Out of curiosity why is this needed?

DavidMCerdeira · 2025-12-16T14:25:14Z

src/platform/tc4dx/tc4dx_desc.c

+const uint32_t plat_int_size = sizeof(plat_ints) / 4;
+#endif
+
+const struct plat_device dev_array[] = {


Bao needs to explicitly lock access to these peripherals before selectively assigning them to each VM

Signed-off-by: Miguel Silva <[email protected]>

miguelafsilva5 force-pushed the feat/tricore branch 2 times, most recently from f92535a to 57284c8 Compare September 1, 2025 14:05

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Base automatically changed from feat/non-unified-mem to main September 10, 2025 13:32

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miguelafsilva5 marked this pull request as ready for review December 16, 2025 13:43

miguelafsilva5 requested review from DavidMCerdeira, danielRep, josecm and sandro2pinto as code owners December 16, 2025 13:43

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feat(tricore): Initial commit

c5745c5

Signed-off-by: Miguel Silva <[email protected]>

miguelafsilva5 force-pushed the feat/tricore branch from 83500c2 to c5745c5 Compare January 19, 2026 16:36

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		#include <bao.h>

		#define CACHE_MAX_LVL 8 // Does this make sense in all architectures?

		#define IPI_CPU_MSG (0x1460 / 4) /* TODO this is the first GPSR in TC49 */
		#define GSPR_SRC_BASE (0x1460 / 4) /* TODO this is the first GPSR in TC49 */

		-Wstrict-prototypes -Wunused-but-set-variable \
		-Wno-multistatement-macros

feat(tricore): Initial tricore support #242

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miguelafsilva5 commented Aug 29, 2025 •

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