Add BIC immediate, CMHI, CNT, single-precision FMOV and UADDLV to ARM model #210
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This adds the form "fmov Wdd, Snn" to the model, also slightly refactoring the modelling of the existing 64-bit versions.
This currently only adds the .8h version.
aqjune-aws
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Mar 31, 2025
| // MOVI | ||
| if q then | ||
| // MOVI, 128-bit only | ||
| if cmode = word 0b1110 /\ q then |
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This change looks fine to me. This additional guard is necessary because arm_adv_simd_expand_imm can now handle more cases.
pennyannn
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Mar 31, 2025
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I have done the following things:
- Checked the modeling against ARM manual
- Running this PR on my graviton3 machine and I found all modeled instruction variants in the output
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Should these instructions be added to |
This should fix issues pointed out in the code review. The arm/allowed_asm list has been updated for other recently added instructions too.
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Thanks for the eagle-eyed review! I think the new commit fixes all that. I took the chance to add other new instructions that were added recently to the |
pennyannn
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Apr 1, 2025
aqjune-aws
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Apr 2, 2025
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- Checked that the bit formats are equal to what the Arm doc describes.
- Also checked that cosimulator does not fail for > 10 minutes, after excluding all scalar instructions to focus on possibly affected vector instructions.
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Probably we can merge after Nevine's patch is merged first, since her PR is reviewed first..? |
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