This repository contains the files for an FPGA design project, developed for the EE2026 course. The project implements a graphing calculator on a Xilinx Artix-7 FPGA.
The calculator is capable of:
- Fixed-Point Arithmetic: Performs calculations using Q16.16 fixed-point number representation.
- Polynomial Graphing: Graphs polynomial equations up to degree 3 (e.g.,
y = ax^3 + bx^2 + cx + d). - Graph Interaction: Allows users to zoom in/out and pan the graph view for better visualization.
- Table of Values: Generates and displays a table of (x, y) values based on the entered polynomial equation.
- Integral Calculation: Computes the definite integral of the polynomial between user-specified lower and upper bounds.
- Integral Shading: Visually represents the calculated integral by shading the corresponding area under the curve on the graph.
- FPGA: Xilinx Artix-7 (Device:
xc7a35tcpg236-1) - Software: Xilinx Vivado 2018.2
- Ensure you have Xilinx Vivado 2018.2 installed.
- Open the project file:
FDP.xprin Vivado. - Run Synthesis: Use the
synth_1run configuration. - Run Implementation: Use the
impl_1run configuration. - Generate Bitstream.
- Program the target FPGA device using the generated bitstream.
.gitignore: Specifies intentionally untracked files by Git.FDP.xpr: Vivado project file.FDP.srcs/: Contains project source files (Verilog, IP cores, constraints).sources_1/: HDL source files, imported files, and IP configurations.constrs_1/: Constraint files (e.g.,.xdc).sim_1/: Simulation source files.
FDP.runs/: Stores output files from synthesis and implementation runs.*.pdf: User Guide and Report.archive_project_summary.txt: Summary of archived project contents.
Refer to the User Guide PDF (S2_07_CHENG JIA_CHOY WAYNE_DANIEL KWAN_HO WEI_User_Guide_ReportPersonal and Team Improvement.pdf) for detailed instructions on how to operate the graphing calculator, including entering equations, setting bounds, and using the zoom/pan features.