Adjust for rebase on top of dmac-api

hal/src/dmac/channel/mod.rs

@@ -40,8 +40,9 @@ use atsamd_hal_macros::{hal_cfg, hal_macro_helper};
 
 use super::{
     dma_controller::{ChId, PriorityLevel, TriggerAction, TriggerSource},
+    sram::DmacDescriptor,
     transfer::{BufferPair, Transfer},
-    Buffer, DmacDescriptor, Error,
+    Buffer, Error,
 };
 use crate::typelevel::{Is, Sealed};
 use modular_bitfield::prelude::*;

hal/src/dmac/mod.rs

@@ -353,7 +353,7 @@ macro_rules! get {
 pub const NUM_CHANNELS: usize = with_num_channels!(get);
 
 /// DMAC SRAM registers
-mod sram {
+pub(crate) mod sram {
     #![allow(dead_code, unused_braces)]
 
     use super::{BeatSize, NUM_CHANNELS};
@@ -391,7 +391,7 @@ mod sram {
     /// Descriptor representing a SRAM register. Datasheet section 19.8.2
     #[derive(Clone, Copy)]
     #[repr(C, align(16))]
-    pub(super) struct DmacDescriptor {
+    pub struct DmacDescriptor {
         pub(super) btctrl: BlockTransferControl,
         pub(super) btcnt: u16,
         pub(super) srcaddr: *const (),
@@ -400,37 +400,37 @@ mod sram {
     }
 
     impl DmacDescriptor {
-        pub(crate) const fn default() -> Self {
+        pub const fn default() -> Self {
             Self {
-                btctrl: BlockTransferControl::default(),
+                btctrl: BlockTransferControl::new(),
                 btcnt: 0,
                 srcaddr: 0 as *mut _,
                 dstaddr: 0 as *mut _,
                 descaddr: 0 as *mut _,
             }
         }
-        pub(crate) fn next_descriptor(&self) -> *const DmacDescriptor {
+        pub fn next_descriptor(&self) -> *const DmacDescriptor {
             self.descaddr
         }
 
-        pub(crate) fn set_next_descriptor(&mut self, next: *mut DmacDescriptor) {
+        pub fn set_next_descriptor(&mut self, next: *mut DmacDescriptor) {
             self.descaddr = next;
         }
 
-        pub(crate) fn beat_count(&self) -> u16 {
+        pub fn beat_count(&self) -> u16 {
             self.btcnt
         }
     }
 
     /// Writeback section. This static variable should never be written to in an
     /// interrupt or thread context.
     pub(super) static mut WRITEBACK: [DmacDescriptor; NUM_CHANNELS] =
-        [DEFAULT_DESCRIPTOR; NUM_CHANNELS];
+        [DmacDescriptor::default(); NUM_CHANNELS];
 
     /// Descriptor section. This static variable should never be written to in
     /// an interrupt or thread context.
     pub(super) static mut DESCRIPTOR_SECTION: [DmacDescriptor; NUM_CHANNELS] =
-        [DEFAULT_DESCRIPTOR; NUM_CHANNELS];
+        [DmacDescriptor::default(); NUM_CHANNELS];
 }
 
 pub mod channel;

hal/src/dmac/transfer.rs

@@ -85,7 +85,8 @@
 use super::{
     channel::{AnyChannel, Busy, CallbackStatus, Channel, ChannelId, InterruptFlags, Ready},
     dma_controller::{ChId, TriggerAction, TriggerSource},
-    sram, Error, Result,
+    sram::{self, DmacDescriptor},
+    Error, Result,
 };
 use crate::typelevel::{Is, Sealed};
 use core::{ptr::null_mut, sync::atomic};
@@ -374,7 +375,7 @@ where
         // belonging to OUR channel. We assume this is the only place
         // in the entire library that this section of the array
         // will be accessed.
-        let descriptor = &mut DESCRIPTOR_SECTION[id];
+        let descriptor = &mut sram::DESCRIPTOR_SECTION[id];
 
         // Enable support for circular transfers. If circular_xfer is true,
         // we set the address of the "next" block descriptor to actually
@@ -396,7 +397,7 @@ where
     pub(super) unsafe fn link_next(next: *mut DmacDescriptor) {
         let id = <C as AnyChannel>::Id::USIZE;
 
-        DESCRIPTOR_SECTION[id].descaddr = next;
+        sram::DESCRIPTOR_SECTION[id].descaddr = next;
     }
 
     /// Generate a [`DmacDescriptor`], and write it to the provided descriptor

hal/src/sercom/dma.rs

@@ -11,8 +11,9 @@ use crate::{
     dmac::{
         self,
         channel::{AnyChannel, Busy, CallbackStatus, Channel, InterruptFlags, Ready},
+        sram::DmacDescriptor,
         transfer::BufferPair,
-        Beat, Buffer, DmacDescriptor, Error, Transfer, TriggerAction,
+        Beat, Buffer, Error, Transfer, TriggerAction,
     },
     sercom::{
         i2c::{self, I2c},

hal/src/sercom/i2c/impl_ehal.rs

@@ -103,7 +103,7 @@ impl<C: AnyConfig> i2c::I2c for I2c<C> {
 #[cfg(feature = "dma")]
 mod dma {
     use super::*;
-    use crate::dmac::{AnyChannel, DmacDescriptor, Ready};
+    use crate::dmac::{sram::DmacDescriptor, AnyChannel, Ready};
     use crate::sercom::dma::{read_dma_linked, write_dma_linked, SercomPtr, SharedSliceBuffer};
     use crate::sercom::{self, Sercom};
 

hal/src/sercom/spi/impl_ehal.rs

@@ -126,7 +126,7 @@ where
 #[cfg(feature = "dma")]
 mod dma {
     use super::*;
-    use crate::dmac::{channel::Ready, AnyChannel, Beat, Buffer, DmacDescriptor};
+    use crate::dmac::{channel::Ready, sram::DmacDescriptor, AnyChannel, Beat, Buffer};
     use crate::sercom::dma::{
         read_dma, read_dma_linked, write_dma, write_dma_linked, SercomPtr, SharedSliceBuffer,
     };