Implicit conversion to enum

Signed-off-by: Ryszard Rozak <[email protected]>
antmicro · Oct 7, 2024 · cd99c36 · cd99c36
1 parent 22fa9f8
commit cd99c36
Showing 1 changed file with 6 additions and 3 deletions.
diff --git a/src/riscv_asm_program_gen.sv b/src/riscv_asm_program_gen.sv
@@ -1216,7 +1216,8 @@ class riscv_asm_program_gen extends uvm_object;
     gen_signature_handshake(instr, CORE_STATUS, INSTR_FAULT_EXCEPTION);
     gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE));
     if (cfg.pmp_cfg.enable_pmp_exception_handler) begin
-      cfg.pmp_cfg.gen_pmp_exception_routine({cfg.gpr, cfg.scratch_reg, cfg.pmp_reg[0],
+       riscv_instr_pkg::riscv_reg_t arg;
+      cfg.pmp_cfg.gen_pmp_exception_routine({arg, cfg.scratch_reg, cfg.pmp_reg[0],
                                              cfg.pmp_reg[1]},
                                             INSTRUCTION_ACCESS_FAULT,
                                             instr);
@@ -1232,7 +1233,8 @@ class riscv_asm_program_gen extends uvm_object;
     gen_signature_handshake(instr, CORE_STATUS, LOAD_FAULT_EXCEPTION);
     gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE));
     if (cfg.pmp_cfg.enable_pmp_exception_handler) begin
-      cfg.pmp_cfg.gen_pmp_exception_routine({cfg.gpr, cfg.scratch_reg, cfg.pmp_reg[0],
+       riscv_instr_pkg::riscv_reg_t arg;
+      cfg.pmp_cfg.gen_pmp_exception_routine({arg, cfg.scratch_reg, cfg.pmp_reg[0],
                                              cfg.pmp_reg[1]},
                                             LOAD_ACCESS_FAULT,
                                             instr);
@@ -1248,7 +1250,8 @@ class riscv_asm_program_gen extends uvm_object;
     gen_signature_handshake(instr, CORE_STATUS, STORE_FAULT_EXCEPTION);
     gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE));
     if (cfg.pmp_cfg.enable_pmp_exception_handler) begin
-      cfg.pmp_cfg.gen_pmp_exception_routine({cfg.gpr, cfg.scratch_reg, cfg.pmp_reg[0],
+       riscv_instr_pkg::riscv_reg_t arg;
+      cfg.pmp_cfg.gen_pmp_exception_routine({arg, cfg.scratch_reg, cfg.pmp_reg[0],
                                              cfg.pmp_reg[1]},
                                             STORE_AMO_ACCESS_FAULT,
                                             instr);