Update mgmt_core config

openlane/mgmt_core/config.tcl

@@ -5,24 +5,27 @@ set ::env(DESIGN_NAME) mgmt_core
 set ::env(CLOCK_PORT) "clock"
 set ::env(CLOCK_PERIOD) "50"
 set ::env(SYNTH_STRATEGY) 2
+set ::env(SYNTH_MAX_FANOUT) 4
 
+set ::env(FP_PDN_VPITCH) 50
 set ::env(PDN_CFG) $script_dir/pdn.tcl
 
 set ::env(FP_VERTICAL_HALO) 6
 set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
 set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 2600 1100"
+set ::env(DIE_AREA) "0 0 2150 850"
 
 
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(PL_TARGET_DENSITY) 0.37
+set ::env(PL_TARGET_DENSITY) 0.52
+set ::env(PL_TARGET_DENSITY_CELLS) 0.38
 set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
 set ::env(CELL_PAD) 8
 
 set ::env(GLB_RT_ADJUSTMENT) 0
 set ::env(GLB_RT_TILES) 14
 
-set ::env(DIODE_INSERTION_STRATEGY) 0
+set ::env(DIODE_INSERTION_STRATEGY) 1
 
 set ::env(VERILOG_FILES) "\
 	$script_dir/../../verilog/rtl/defines.v\
@@ -34,7 +37,8 @@ set ::env(VERILOG_FILES) "\
 	$script_dir/../../verilog/rtl/housekeeping_spi.v"
 
 set ::env(VERILOG_FILES_BLACKBOX) "\
-	$script_dir/../../verilog/gl/DFFRAM.gl.v
+	$script_dir/../../verilog/rtl/defines.v\
+	$script_dir/../../verilog/rtl/DFFRAM.v
 	$script_dir/../../verilog/rtl/digital_pll.v"
 
 set ::env(EXTRA_LEFS) "\

openlane/mgmt_core/macro_placement.cfg

@@ -1,2 +1,2 @@
-pll 14.360 501.110 N
-soc.soc_mem.mem.SRAM 395.345 191.120 N
+pll 14.36 256.400 N
+soc.soc_mem.mem.SRAM 1333.285 123.980 N

openlane/mgmt_core/pdn.tcl

@@ -25,7 +25,7 @@ pdngen::specify_grid macro {
     connect {{met4_PIN_ver met5}}
 }
 
-set ::halo 10
+set ::halo 5
 
 # POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
 set ::rails_start_with "POWER" ;