Skip to content
View andreaskurth's full-sized avatar
  • Switzerland
  • 18:23 (UTC +01:00)

Sponsoring

@dalance
@jesseduffield

Block or report andreaskurth

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. lowRISC/opentitan lowRISC/opentitan Public

    OpenTitan: Open source silicon root of trust

    SystemVerilog 2.6k 772

  2. lowRISC/ibex lowRISC/ibex Public

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1.4k 543

  3. pulp-platform/axi pulp-platform/axi Public

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog 1.1k 265

  4. pulp-platform/hero pulp-platform/hero Public

    Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software …

    SystemVerilog 94 24

  5. memora-rs memora-rs Public

    Memora: Build Artifact Cache for Git Repositories

    Rust 8 3