Parameterizable AVL dacfifo and parallel pack core

[bluncan]

PR Description

library: adxcvr: Sync inputs for Agilex - to ease the timing

library: util_pack: pack_shell: Parallelized the prefix sum calculation:

• The old algorithm used NUMBER_OF_SAMPLES adders in series to calculate the prefix sum and this caused a timing violation on some Intel boards at high JESD204 lane rates when NUMBER_OF_SAMPLES was large (e.g 64).
• The new algorithm uses at most log2(NUMBER_OF_SAMPLES) adders in series for the right most element but more adders overall
• The new algorithm is opt-in and the old one is the default one.

projects: common: fm87: Add external ddr instantiation with avl_dacfifo - needed when using the FMC2 port

This PR is needed for AD9084 support on Agilex.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones