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ad_gmsl2eth_sl: Rework assign_bd_address #1425

Merged
merged 3 commits into from
Sep 24, 2024
Merged

ad_gmsl2eth_sl: Rework assign_bd_address #1425

merged 3 commits into from
Sep 24, 2024

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gastmaier
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@gastmaier gastmaier commented Aug 23, 2024

PR Description

Rework assign_bd_address to only provide objects to assign instead of providing a explicit target_address_space.
Aims to fix the error obtained on the CI:

### assign_bd_address -target_address_space /corundum/m_axi_dma [get_bd_addr_segs sys_ps8/SAXIGP0/HPC0_LPS_OCM] -force
ERROR: [BD 5-309] Master address space </corundum/m_axi_dma> does not exist.

    while executing
"source ../common/ad_gmsl2eth_sl_bd.tcl"
    (file "system_bd.tcl" line 8)

I was not able to replicate the error locally.
Synthesized the changed project locally.

Remove duplicated content on doc page.

48c3dff fixes:

CRITICAL WARNING: [xilinx.com:ip:smartconnect:1.0-1] system_axi_hpc0_interconnect_0: The device(s) attached to /S00_AXI do not share a common clock domain with this smartconnect instance. Modify the clock domain values of the attached device(s) or re-customize this AXI SmartConnect instance to add a new clock pin and connect it to the same clock source of the IP attached to /S00_AXI to prevent further clock DRC violations.

b62d551 fixes:

CRITICAL WARNING: [Designutils 20-1280] Could not find module 'eth_xcvr_gth_channel'. The XDC file /media/data/work_sarpadi/pers_work/wrep_4/hdl/projects/ad_gmsl2eth_sl/k26/ad_gmsl2eth_sl_k26.gen/sources_1/bd/system/ip/system_corundum_0/corundum.srcs/sources_1/ip/eth_xcvr_gth_channel/synth/eth_xcvr_gth_channel.xdc will not be read for any cell of this module.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@bia1708
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bia1708 commented Aug 27, 2024

RetriggerCI

adi_project_run ad_gmsl2eth_sl_k26
reset_msg_config -id {Designutils 20-1280} -default_severity
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why are you resetting?

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Resetting after the synthesis, so it won't affect other projects.

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On the last commit, I remove the dangling IP instead, not requiring to downgrade this error message

@alin724 alin724 self-requested a review September 24, 2024 07:46
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LGTM

Only provide objects to assign instead of providing a explicit
target_address_space.
Add port name to ad_mem_hpc0_interconnect. remove data width.

Signed-off-by: Jorge Marques <[email protected]>
Infer address space of m_axi_dma after creating the intf
xilinx.com:interface:aximm:1.0
Previously, would inherit from the inferred prior to
ipx::remove_all_bus_interface [ipx::current_core]
However, vivado shall infer other intf like
analog.com:interface:if_xcvr_cm:1.0
as observed in the CI with the other libs/intfs in cache,
and not infer the addr space at that point.

Call adi_add_bus_clk once with all buses, to generate a single bus
abstraction for the clk and rst signal, which caused issues with the
association of the signals with the interfaces.
Rename core_clk and core_rst to clk and rst.

Remove eth_xcvr_gth_channel during the corundum IP build.
Even though both eth_xcvr_gth_channel and eth_xcvr_gth_full are created
by the corundum script, only the latter is used on the design at our
configuration.
Resolves Designutils 20-1280 critical warning

Signed-off-by: Jorge Marques <[email protected]>
@gastmaier gastmaier merged commit eacb6b2 into main Sep 24, 2024
0 of 3 checks passed
@gastmaier gastmaier deleted the ad_gmsl2eth_sl-fix branch September 24, 2024 19:49
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4 participants