ad411x_ad717x: DRDY Interrupt

docs/projects/ad411x_ad717x/index.rst

@@ -155,6 +155,10 @@ The Software GPIO number is calculated as follows:
      - (from FPGA view)
      -
      - DE10-Nano
+   * - spi_miso
+     - INPUT
+     - 34
+     - 2
    * - error
      - INPUT
      - 33
@@ -259,6 +263,9 @@ HDL related
    * - SYSID_ROM
      - :git-hdl:`library/sysid_rom <library/sysid_rom>`
      - :ref:`here <axi_sysid>`
+   * - UTIL_SIGMA_DELTA_SPI
+     - :git-hdl:`library/util_sigma_delta_spi <library/util_sigma_delta_spi>`
+     - :dokuwiki:`[Wiki] <resources/fpga/peripherals/util_sigma_delta_spi>`
 
 
 -  :ref:`SPI Engine Framework documentation <spi_engine>`

library/util_sigma_delta_spi/Makefile

@@ -15,4 +15,6 @@ XILINX_DEPS += ../spi_engine/interfaces/spi_engine_rtl.xml
 
 XILINX_INTERFACE_DEPS += spi_engine/interfaces
 
+INTEL_DEPS += util_sigma_delta_spi_hw.tcl
+
 include ../scripts/library.mk

library/util_sigma_delta_spi/util_sigma_delta_spi_hw.tcl

@@ -0,0 +1,47 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+#################################################################################
+
+# ip
+
+package require qsys 14.0
+source ../../scripts/adi_env.tcl
+source ../scripts/adi_ip_intel.tcl
+
+ad_ip_create util_sigma_delta_spi {UTIL SIGMA DELTA SPI}
+set_module_property ELABORATION_CALLBACK p_elaboration
+ad_ip_files util_sigma_delta_spi [list \
+  util_sigma_delta_spi.v]
+
+# parameters
+
+ad_ip_parameter IDLE_TIMEOUT INTEGER 63
+ad_ip_parameter CS_PIN INTEGER 0
+ad_ip_parameter NUM_OF_CS INTEGER 2
+
+proc p_elaboration {} {
+
+  set num_cs [get_parameter_value NUM_OF_CS]
+# interfaces
+
+# clock and reset interface
+
+  ad_interface clock clk    input 1
+  ad_interface reset resetn input 1 if_clk
+
+  ad_interface signal spi_active input 1 active
+  ad_interface signal data_ready output 1 if_pwm
+
+  ad_interface clock s_sclk   input 1 sclk
+  ad_interface signal s_sdo   input 1 sdo
+  ad_interface signal s_sdo_t input 1 sdo_t
+  ad_interface signal s_sdi   output 1 sdi
+  ad_interface signal s_cs    input $num_cs cs
+
+  ad_interface clock m_sclk   output 1
+  ad_interface signal m_sdo   output 1
+  ad_interface signal m_sdo_t output 1
+  ad_interface signal m_sdi   input 1
+  ad_interface signal m_cs    output $num_cs
+}