Design-of-Phase-Locked-Loop

Block Diagram of PLL Architecture:

NOTE:

To build the complete PLL architecture, we'll use some standard gates, such as AND, NOR, and NOT.
We'll also use two types of D Flip-Flops: DFF_Reset and TSPC DFF.
Refer Directory: Prerequisite Standard Gates & Circuits

Role of PFD in PLL:

1. The PFD operates by receiving two input signals (reference and divider outputs), and its output transitions help detect both phase and frequency differences.​
2. Digital D-type flip-flops (DFFs) are used in a typical PFD implementation, for robust operation under low voltage (1.0–1.2V) and high-speed switching in the 45nm process node.

Role of CP in PLL:

1. It converts the digital phase/frequency error pulses from the detector into analog current pulses.
2. It pumps the error current into the loop filter, which integrates it to produce the smooth DC control voltage ($\boldsymbol{V}_{\mathbf{c}}$) that tunes the VCO frequency.

Role of CSVCO in PLL:

1. The current-starved VCO’s oscillation frequency is controlled by the bias current, allowing precise tuning of the output frequency in response to the control voltage from the PLL.
2. It limits the current through the delay stages, reducing overall power consumption compared to a regular ring VCO.
3. Its design is compact and fully CMOS-compatible, making it ideal for on-chip PLL implementations.

Role of AD in PLL:

1. Frequency Division: It divides the VCO output frequency by a programmable factor to generate a lower frequency for comparison with the reference clock in the phase detector.
2. Wide Frequency Range: Enables the PLL to lock onto a much higher VCO frequency while maintaining a manageable reference frequency.
3. Reduced Power and Area: Asynchronous (ripple) dividers are simpler and consume less power compared to synchronous dividers, making them suitable for high-frequency applications.