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Given the following VHDL design (vector_assign.vhd):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vector_assign is
Port (
a : in std_ulogic_vector(3 downto 0);
b : out std_ulogic_vector(3 downto 0)
);
end vector_assign;
architecture Behavioral of vector_assign is
begin
b <= a;
end Behavioral;
And the following test bench (tb.vhd):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb is
end tb;
architecture Behavioral of tb is
component vector_assign
Port (
a : in std_ulogic_vector(3 downto 0);
b : out std_ulogic_vector(3 downto 0)
);
end component;
signal a : std_ulogic_vector(3 downto 0) := (others => '0');
signal b : std_ulogic_vector(3 downto 0);
begin
uut: vector_assign
Port map (
a => a,
b => b
);
stimulus: process
begin
a <= "0001";
wait for 10 ns;
wait;
end process;
end Behavioral;
When we create a VCD file with the following script:
ghdl -a vector_assign.vhd
ghdl -a tb.vhd
ghdl -e tb
ghdl -r tb --vcd=ghdl_simulation.vcd
If we elaborate the VHDL design (vector_assign.vhd) and load the GHDL generated VCD with the following yosys script:
The lack of white space between the variable a and the bit range ([3:0]) is the issue.
Note gtkwave loads both VCDs without issue and they are equivalent.
The specification of VCD (See 21.7.2.1 Syntax of 4-state VCD file in IEEE Std 1800™-2017) seems to allow both ways of $var specification.
Version
Yosys 0.45+139 (git sha1 e7fc1b0cc, g++ 13.2.0 -fPIC -O3)
On which OS did this happen?
Linux
Reproduction Steps
Given the following VHDL design (
vector_assign.vhd
):And the following test bench (
tb.vhd
):When we create a VCD file with the following script:
If we elaborate the VHDL design (
vector_assign.vhd
) and load the GHDL generated VCD with the following yosys script:We get the following error:
Preliminary analysis
The VCD declarations of the variables differ:
yosys VCD (
yosys_simulation.vcd
):$var wire 4 n1 a [3:0] $end
GHDL VCD (
ghdl_simulation.vcd
):$var reg 4 ! a[3:0] $end
The lack of white space between the variable
a
and the bit range ([3:0]
) is the issue.Note
gtkwave
loads both VCDs without issue and they are equivalent.The specification of VCD (See 21.7.2.1 Syntax of 4-state VCD file in IEEE Std 1800™-2017) seems to allow both ways of
$var
specification.The relevant function is
FstData::extractVarNames
in https://github.com/YosysHQ/yosys/blob/main/kernel/fstdata.cc#L112.Expected Behavior
Actual Behavior
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