[Bug report] Attempt to access a non-implemented CSR should raise an illegal instruction

[flaviens]

Hi there!

I think I found a bug in Picorv32. Please let me know if it is incorrect.

Brief bug description

Accessing non-existent CSR does not raise an illegal instruction, but instead hangs after fetching the next instruction.

The RISC-V specification says:

Attempts to access a non-existent CSR raise an illegal instruction exception.

Tested parameters

I used the following parameters:

.ENABLE_COUNTERS      (1),
.ENABLE_COUNTERS64    (1),
.ENABLE_REGS_16_31    (1),
.ENABLE_REGS_DUALPORT (1),
.LATCHED_MEM_RDATA    (0),
.TWO_STAGE_SHIFT      (1),
.BARREL_SHIFTER       (0),
.TWO_CYCLE_COMPARE    (0),
.TWO_CYCLE_ALU        (0),
.COMPRESSED_ISA       (1),
.CATCH_MISALIGN       (1),
.CATCH_ILLINSN        (1),
.ENABLE_PCPI          (0),
.ENABLE_MUL           (1),
.ENABLE_FAST_MUL      (0),
.ENABLE_DIV           (1),
.ENABLE_IRQ           (0),
.ENABLE_IRQ_QREGS     (1),
.ENABLE_IRQ_TIMER     (1),
.ENABLE_TRACE         (0),
.REGS_INIT_ZERO       (0),
.MASKED_IRQ           (32'h 0000_0000),
.LATCHED_IRQ          (32'h ffff_ffff),
.PROGADDR_RESET       (32'h 8000_0000),
.PROGADDR_IRQ         (32'h 0000_0010),
.STACKADDR            (32'h ffff_ffff)

Example snippet

Here is an example snippet, given that, as specified by the RISC-V specification:

In systems without S-mode, the medeleg and mideleg registers should not exist.

The program below hangs after fetching the first nop.

  .section ".text.init","ax",@progbits
  .globl _start
  .align 2
_start:

  csrrw zero, medeleg, zero

  nop
  nop

infinite_loop1:
  j infinite_loop1

Thanks!
Flavien