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[Bug] History-dependent <code>lb</code> mismatch

Status: Open.

#283 In YosysHQ/picorv32;

· canxin121 opened on Nov 24, 2025

spimemio never enters dual-lane DDR despite README listing it as valid

Status: Open.

#280 In YosysHQ/picorv32;

· 5S-MOHAMED-SHABAIK opened on Oct 21, 2025

CATCH_MISALIGN: misaligned store still drives mem_wstrb on AXI-Lite

Status: Open.

#279 In YosysHQ/picorv32;

· canxin121 opened on Oct 21, 2025

CATCH_MISALIGN: misaligned load still writes destination register

Status: Open.

#278 In YosysHQ/picorv32;

· canxin121 opened on Oct 21, 2025

Inconsistent Return Address Timing in PicoSoC IRQ Handler

Status: Open.

#277 In YosysHQ/picorv32;

· 5S-MOHAMED-SHABAIK opened on Oct 2, 2025

Incomplete cross-compilation tool path in picosoc Makefile

Status: Open.

#275 In YosysHQ/picorv32;

· RakeshpatilLB opened on Jul 4, 2025

picosoc on arty A7100T

Status: Open.

#273 In YosysHQ/picorv32;

· RakeshpatilLB opened on Jun 19, 2025

Deleting redundant Verilog code can unexpectedly increase LUT utilization

Status: Open.

#270 In YosysHQ/picorv32;

· xiaguangbo opened on Mar 27, 2025

Synthesis Bug : Mismatch in PCPI INSN and Memory Address

Status: Open.

#269 In YosysHQ/picorv32;

· rsar97 opened on Jan 27, 2025

Is the CPU in PicoRV32 Implemented as a 5-Stage Pipeline?

Status: Open.

#268 In YosysHQ/picorv32;

· alihkousha opened on Dec 15, 2024

Help regarding Simulation of PicoRV32 in vivado

Status: Open.

#267 In YosysHQ/picorv32;

· Tanishqgithub opened on Jul 11, 2024

Fmax and latency on PicoRV32

Status: Open.

#265 In YosysHQ/picorv32;

· SyedFahimuddinAlavi opened on Jul 2, 2024