examples: add icesugar support

examples/icesugar/Makefile

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+#  NERV -- Naive Educational RISC-V Processor
+#
+#  Copyright (C) 2020  N. Engelhardt <[email protected]>
+#  Copyright (C) 2020  Claire Xenia Wolf <[email protected]>
+#
+#  Permission to use, copy, modify, and/or distribute this software for any
+#  purpose with or without fee is hereby granted, provided that the above
+#  copyright notice and this permission notice appear in all copies.
+#
+#  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+ICELINK_DIR=$(shell df | grep iCELink | awk '{print $$6}')
+${warning iCELink path: $(ICELINK_DIR)}
+
+TOOLCHAIN_PREFIX?=riscv64-unknown-elf-
+
+test: firmware.hex testbench
+	vvp -N testbench +vcd
+
+firmware.elf: firmware.s firmware.c
+	$(TOOLCHAIN_PREFIX)gcc -march=rv32i -mabi=ilp32 -Os -Wall -Wextra -Wl,-Bstatic,-T,sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $^
+
+firmware.hex: firmware.elf
+	$(TOOLCHAIN_PREFIX)objcopy -O verilog $< /dev/stdout | sed -r 's,(..) (..) (..) (..),\4\3\2\1,g' > $@
+
+testbench: testbench.sv ../../nerv.sv ../../nervsoc.sv top.v firmware.hex
+	iverilog -o testbench -D STALL -D NERV_DBGREGS testbench.sv ../../nerv.sv ../../nervsoc.sv top.v
+
+design.json: ../../nerv.sv ../../nervsoc.sv top.v firmware.hex
+	yosys -l design_ys.log -p 'synth_ice40 -top top -json $@' ../../nerv.sv ../../nervsoc.sv top.v
+
+design.asc: design.json icesugar.pcf
+	nextpnr-ice40 -l design_pnr.log --up5k --package sg48 --asc design.asc --pcf icesugar.pcf --json design.json --placer heap
+
+design.bin: design.asc
+	icepack $< $@
+
+prog: design.bin
+	@if [ -d '$(ICELINK_DIR)' ]; \
+	then \
+		cp $< $(ICELINK_DIR); \
+	else \
+		echo "iCELink not found"; \
+		exit 1; \
+	fi
+
+show:
+	gtkwave testbench.vcd testbench.gtkw >> gtkwave.log 2>&1 &
+
+clean:
+	rm -rf firmware.elf firmware.hex testbench testbench.vcd gtkwave.log
+	rm -rf design.json design.asc design.bin design_ys.log design_pnr.log

examples/icesugar/README.md

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+# SOC example for iCESugar
+
+![iCESugar SOC](../icebreaker/icebreaker_soc.png)
+
+# Demo
+
+Counts on the 8 LEDs.
+
+```
+make prog
+```
+
+# SOC
+
+The SOC instantiates [nervsoc](../../nervsoc.sv).
+
+* [top.v](top.v) Connects clock input and 8 LEDs on the iCESugar and provides power on reset
+* [sections.lds](sections.lds) sets flash and ram to 4k each.
+* [firmware.s](firmware.s) initialises registers, copies data section, initialises bss and starts main
+* [firmware.c](firmware.c) flashes the LEDs.

examples/icesugar/firmware.c

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+/*
+ *  NERV -- Naive Educational RISC-V Processor
+ *
+ *  Copyright (C) 2020  Miodrag Milanovic <[email protected]>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include <stdint.h>
+
+void delay(uint32_t count)
+{
+	while(count-->0) {
+		__asm__ volatile ("nop");
+	}
+}
+
+int main()
+{
+	volatile uint32_t *leds = (void*)0x01000000;
+    *leds = 0;
+	uint32_t cnt = 0;
+	while(1)
+	{
+		delay(100000);
+		*leds = cnt++;
+	}
+	return 0;
+}

examples/icesugar/firmware.s

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+/*
+ *  NERV -- Naive Educational RISC-V Processor
+ *
+ *  Copyright (C) 2020  Claire Xenia Wolf <[email protected]>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+.section .text
+.global main
+.global _start
+_start:
+addi x1, zero, 0
+addi x2, zero, 0
+addi x3, zero, 0
+addi x4, zero, 0
+addi x5, zero, 0
+addi x6, zero, 0
+addi x7, zero, 0
+addi x8, zero, 0
+addi x9, zero, 0
+addi x10, zero, 0
+addi x11, zero, 0
+addi x12, zero, 0
+addi x13, zero, 0
+addi x14, zero, 0
+addi x15, zero, 0
+addi x16, zero, 0
+addi x17, zero, 0
+addi x18, zero, 0
+addi x19, zero, 0
+addi x20, zero, 0
+addi x21, zero, 0
+addi x22, zero, 0
+addi x23, zero, 0
+addi x24, zero, 0
+addi x25, zero, 0
+addi x26, zero, 0
+addi x27, zero, 0
+addi x28, zero, 0
+addi x29, zero, 0
+addi x30, zero, 0
+addi x31, zero, 0
+
+# copy data section
+la a0, _sidata
+la a1, _sdata
+la a2, _edata
+bge a1, a2, end_init_data
+loop_init_data:
+lw a3, 0(a0)
+sw a3, 0(a1)
+addi a0, a0, 4
+addi a1, a1, 4
+blt a1, a2, loop_init_data
+end_init_data:
+
+# zero-init bss section
+la a0, _sbss
+la a1, _ebss
+bge a0, a1, end_init_bss
+loop_init_bss:
+sw zero, 0(a0)
+addi a0, a0, 4
+blt a0, a1, loop_init_bss
+end_init_bss:
+
+# place SP at the end of RAM
+li sp, 0x00001000
+
+# call main
+call main
+
+# halt
+ebreak

examples/icesugar/icesugar.pcf

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+# For the iCESugar Board (iCE40UP5K-QFN48)
+
+#set_io LED_G 41
+#set_io LED_R 40
+set_io LEDG_N 41
+set_io LEDR_N 40
+set_io LED_B 39
+
+set_io SW[0] 18
+set_io SW[1] 19
+set_io SW[2] 20
+set_io SW[3] 21
+
+set_io CLK   35
+
+set_io RX    4
+set_io TX    6
+
+set_io USB_DP       10
+set_io USB_DN       9
+set_io USB_PULLUP   11
+
+# PMOD 1
+#set_io P1_1     10
+#set_io P1_2     6
+#set_io P1_3     3
+#set_io P1_4     48
+#set_io P1_9     47
+#set_io P1_10    2
+#set_io P1_11    4
+#set_io P1_12    9
+# PMOD-LED attached to PMOD 1
+set_io LED5    10
+set_io LED4    6
+set_io LED3    3
+set_io LED2    48
+set_io LED1    47
+set_io LED6    2
+set_io LED7    4
+set_io LED8    9
+
+
+# PMOD 2
+set_io P2_1     46
+set_io P2_2     44
+set_io P2_3     42
+set_io P2_4     37
+set_io P2_9     36
+set_io P2_10    38
+set_io P2_11    43
+set_io P2_12    45
+
+# PMOD 3
+set_io P3_1     34
+set_io P3_2     31
+set_io P3_3     27
+set_io P3_4     25
+set_io P3_9     23
+set_io P3_10    26
+set_io P3_11    28
+set_io P3_12    32
+
+# PMOD 4
+set_io P4_1     21
+set_io P4_2     20
+set_io P4_3     19
+set_io P4_4     18
+
+#spi
+set_io SPI_SS   16
+set_io SPI_SCK  15
+set_io SPI_MOSI 17
+set_io SPI_MISO 14

examples/icesugar/sections.lds

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+MEMORY
+{
+    FLASH(xr)       : ORIGIN = 0x00000000, LENGTH = 0x001000
+    RAM  (rw)       : ORIGIN = 0x00000000, LENGTH = 0x001000
+}
+
+SECTIONS {
+    /* The program code and other data goes into FLASH */
+    .text :
+    {
+        . = ALIGN(4);
+        *(.text)           /* .text sections (code) */
+        *(.text*)          /* .text* sections (code) */
+        *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+        *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+        *(.srodata)        /* .rodata sections (constants, strings, etc.) */
+        *(.srodata*)       /* .rodata* sections (constants, strings, etc.) */
+        . = ALIGN(4);
+        _etext = .;        /* define a global symbol at end of code */
+        _sidata = _etext;  /* This is used by the startup in order to initialize the .data secion */
+    } >FLASH
+
+
+    /* This is the initialized data section
+    The program executes knowing that the data is in the RAM
+    but the loader puts the initial values in the FLASH (inidata).
+    It is one task of the startup to copy the initial values from FLASH to RAM. */
+    .data : AT ( _sidata )
+    {
+        . = ALIGN(4);
+        _sdata = .;        /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */
+        _ram_start = .;    /* create a global symbol at ram start for garbage collector */
+        . = ALIGN(4);
+        *(.data)           /* .data sections */
+        *(.data*)          /* .data* sections */
+        *(.sdata)           /* .sdata sections */
+        *(.sdata*)          /* .sdata* sections */
+        . = ALIGN(4);
+        _edata = .;        /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */
+    } >RAM
+
+    /* Uninitialized data section */
+    .bss :
+    {
+        . = ALIGN(4);
+        _sbss = .;         /* define a global symbol at bss start; used by startup code */
+        *(.bss)
+        *(.bss*)
+        *(.sbss)
+        *(.sbss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        _ebss = .;         /* define a global symbol at bss end; used by startup code */
+    } >RAM
+
+    /* this is to define the start of the heap, and make sure we have a minimum size */
+    .heap :
+    {
+        . = ALIGN(4);
+        _heap_start = .;    /* define a global symbol at heap start */
+    } >RAM
+}