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diff --git a/.buildinfo b/.buildinfo
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+# Sphinx build info version 1
+# This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done.
+config: 16e155a25b26e5cbfa5e31c876fc0c81
+tags: 645f666f9bcd5a90fca523b33c5a78b7
diff --git a/.nojekyll b/.nojekyll
diff --git a/README.md b/README.md
@@ -1,5 +1 @@
-# Vitis Video Analytics
-
-## View the [main index file](https://gitenterprise.xilinx.com/techdocs/ivas/blob/master/index.rst)
-
-## View the [HTML](https://pages.gitenterprise.xilinx.com/techdocs/ivas/)
+# View the [HTML](https://pages.gitenterprise.xilinx.com/techdocs/pcie-debug-kmap/)
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diff --git a/...axi4_memory_mapped_master_bridge_write_response_interface_port_descriptions.png b/...axi4_memory_mapped_master_bridge_write_response_interface_port_descriptions.png
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diff --git a/_images/root_port_status_control_register.png b/_images/root_port_status_control_register.png
diff --git a/_images/root_port_system_reset_connection_ultrascale+_devices.jpg b/_images/root_port_system_reset_connection_ultrascale+_devices.jpg
diff --git a/_images/tandem_features.png b/_images/tandem_features.png
diff --git a/_images/top_level_interface_signals.png b/_images/top_level_interface_signals.png
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diff --git a/_images/transfer_error.png b/_images/transfer_error.png
diff --git a/_sources/README.md.txt b/_sources/README.md.txt
@@ -0,0 +1,5 @@
+# Vitis Video Analytics
+
+## View the [main index file](https://gitenterprise.xilinx.com/techdocs/ivas/blob/master/index.rst)
+
+## View the [HTML](https://pages.gitenterprise.xilinx.com/techdocs/ivas/)
diff --git a/...dge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/debug_checklist/images.rst.txt b/...dge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/debug_checklist/images.rst.txt
@@ -0,0 +1,160 @@
+.. _global_signals:
+
+Global Signals
+--------------
+.. image:: images/global_signals.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _axi_slave_interface_signals:
+
+AXI Slave Interface Signals
+---------------------------
+.. image:: images/axi_slave_interface_signals.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _axi_master_interface_signals:
+
+AXI Master Interface Signals
+----------------------------
+.. image:: images/axi_master_interface_signals.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _axi4-lite_control_interface_signals:
+
+AXI4-Lite Control Interface Signals
+-----------------------------------
+.. image:: images/axi4-lite_control_interface_signals.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _axi_bridge_for_pcie_gen3_msi_signals:
+
+AXI Bridge for PCIe Gen3 MSI Signals
+------------------------------------
+.. image:: images/axi_bridge_for_pcie_gen3_msi_signals.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _axi_bridge_for_pcie_gen3_msi-x_signals:
+
+AXI Bridge for PCIe Gen3 MSI-X Signals
+--------------------------------------
+.. image:: images/axi_bridge_for_pcie_gen3_msi-x_signals.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _dma_bridge_subsystem_for_pcie_in_bridge_mode_interrupt_signals:
+
+DMA_Bridge Subsystem for PCIe in Bridge Mode Interrupt Signals
+--------------------------------------------------------------
+.. image:: images/dma_bridge_subsystem_for_pcie_in_bridge_mode_interrupt_signals.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _interrupt_decode_register:
+
+Interrupt Decode Register
+-------------------------
+.. image:: images/interrupt_decode_register.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _phy_status_control_register:
+
+PHY Status_Control Register
+---------------------------
+.. image:: images/phy_status_control_register.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _root_port_status_control_register:
+
+Root Port Status_Control Register
+---------------------------------
+.. image:: images/root_port_status_control_register.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _root_port_error_fifo_read_register:
+
+Root Port Error FIFO Read Register
+----------------------------------
+.. image:: images/root_port_error_fifo_read_register.png
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _clocking_diagram_ultrascale+_devices:
+
+Clocking Diagram (UltraScale+ Devices)
+--------------------------------------
+.. image:: images/clocking_diagram_ultrascale+_devices.jpg
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _endpoint_system_reset_connection_ultrascale+_devices:
+
+Endpoint System Reset Connection (UltraScale+ Devices)
+------------------------------------------------------
+.. image:: images/endpoint_system_reset_connection_ultrascale+_devices.jpg
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+.. _root_port_system_reset_connection_ultrascale+_devices:
+
+Root Port System Reset Connection (UltraScale+ Devices)
+-------------------------------------------------------
+.. image:: images/root_port_system_reset_connection_ultrascale+_devices.jpg
+   :align: center
+
+.. note::
+
+   See the latest version of PG194 for updates
+
+
+
+
+
+
+
diff --git a/...idge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/debug_checklist/index.rst.txt b/...idge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/debug_checklist/index.rst.txt
@@ -0,0 +1,41 @@
+:ref:`global_signals`
+
+
+:ref:`axi_slave_interface_signals`
+
+
+:ref:`axi_master_interface_signals`
+
+
+:ref:`axi4-lite_control_interface_signals`
+
+
+:ref:`axi_bridge_for_pcie_gen3_msi_signals`
+
+
+:ref:`axi_bridge_for_pcie_gen3_msi-x_signals`
+
+
+:ref:`dma_bridge_subsystem_for_pcie_in_bridge_mode_interrupt_signals`
+
+
+:ref:`interrupt_decode_register`
+
+
+:ref:`phy_status_control_register`
+
+
+:ref:`root_port_status_control_register`
+
+
+:ref:`root_port_error_fifo_read_register`
+
+
+:ref:`clocking_diagram_ultrascale+_devices`
+
+
+:ref:`endpoint_system_reset_connection_ultrascale+_devices`
+
+
+:ref:`root_port_system_reset_connection_ultrascale+_devices`
+
diff --git a/.../docs/DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/debug_faq.rst.txt b/.../docs/DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/debug_faq.rst.txt
@@ -0,0 +1,35 @@
+.. _dma_bridge_ip_debug_checklist:
+
+General Debug Checklist
+=======================
+
+* Confirm the clocking architecture is correct
+    * :ref:`clocking_diagram_ultrascale+_devices`
+* Confirm the reset connection is correct
+    * Endpoint:
+        * :ref:`endpoint_system_reset_connection_ultrascale+_devices`
+    * Rootport:
+        * :ref:`root_port_system_reset_connection_ultrascale+_devices`
+* Check the status of Phy Status Control Register 
+    * :ref:`phy_status_control_register`
+* If the issue is related to incoming or outgoing packets from the user logic, check the following interface signals in Vivado ILA
+    * :ref:`axi_slave_interface_signals`
+    * :ref:`axi_master_interface_signals`
+* If there is an issue with bridge register reads or write, check the following interface
+    * :ref:`axi4-lite_control_interface_signals`
+* For interrupt related issues, check the following signals and register:
+    * :ref:`axi_bridge_for_pcie_gen3_msi_signals`
+    * :ref:`axi_bridge_for_pcie_gen3_msi-x_signals`
+    * :ref:`dma_bridge_subsystem_for_pcie_in_bridge_mode_interrupt_signals`
+* For Root Port related issues, check:
+    * :ref:`root_port_status_control_register`
+    * :ref:`root_port_error_fifo_read_register`
+    * :ref:`interrupt_decode_register`
+
+.. note::
+    Please refer to the latest version of PG194 for new updates and more details on referenced signals and registers. 
+
+.. .. _dma_bridge_ip_faqs:
+
+.. General FAQs
+.. ============
diff --git a/...s/DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/debug_gotchas.rst.txt b/...s/DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/debug_gotchas.rst.txt
@@ -0,0 +1,46 @@
+.. _dma_subsystem_bridge_endpoint_debug_gotchas:
+
+Debug Gotchas
+=======================
+
+* An asserted bit in the Interrupt Decode register does not cause the interrupt line to assert unless the corresponding bit in the Interrupt Mask register is also set.
+    * 
+* Available for the DMA/Bridge Subsystem for PCIe in AXI Bridge mode, there is an optional dma_bridge_resetn input pin which allows you to reset all internal Bridge engines and registers as well as all AXI peripherals driven by axi_aresetn and axi_ctl_aresetn pins. When the following parameter is set, dma_bridge_resetn does not need to be asserted during initial link up operation because it will be done automatically by the IP. You must terminate all transactions before asserting this pin. After being asserted, the pin must be kept asserted for a minimum duration of at least equal to the Completion Timeout value (typically 50 ms) to clear any pending transfer that may currently be queued in the data path. To set this parameter, type the following command at the Tcl command line:
+    * set_property -dict [list CONFIG.soft_reset_en {true}] [get_ips <ip_name>]
+* For PCIe® requests with lengths greater than 1 Dword, the size of the data burst on the Master AXI interface will always equal the width of the AXI data bus even when the request received from the PCIe link is shorter than the AXI bus width. s_axi_wstrb can be used to facilitate data alignment to an address boundary.
+    * s_axi_wstrb may equal 0 in the beginning of a valid data cycle and will appropriately calculate an offset to the given address. However, the valid data identified by s_axi_wstrb must be continuous from the first byte enable to the last byte enable.
+* The Bridge core conforms to PCIe® transaction ordering rules. See the PCI-SIG Specifications for the complete rule set. The following behaviors are implemented in the Bridge core to enforce the PCIe transaction ordering rules on the highly-parallel AXI bus of the bridge. 
+    * The bresp to the remote (requesting) AXI4 master device for a write to a remote PCIe device is not issued until the MemWr TLP transmission is guaranteed to be sent on the PCIe link before any subsequent TX-transfers. 
+    * If Relaxed Ordering bit is not set within the TLP header, then a remote PCIe device read to a remote AXI slave is not permitted to pass any previous remote PCIe device writes to a remote AXI slave received by the Bridge core. The AXI read address phase is held until the previous AXI write transactions have completed and bresp has been received for the AXI write transactions. If the Relaxed Ordering attribute bit is set within the TLP header, then the remote PCIe device read is permitted to pass. 
+    * Read completion data received from a remote PCIe device are not permitted to pass any remote PCIe device writes to a remote AXI slave received by the Bridge core prior to the read completion data. The bresp for the AXI write(s) must be received before the completion data is presented on the AXI read data channel.
+* The integrated block for PCI Express® detects a malformed TLP. For the IP configured as an Endpoint core, a malformed TLP results in a fatal error message being sent upstream if error reporting is enabled in the Device Control register.
+    * 
+* The slave bridge monitors AXI read and write burst type inputs to ensure that only the INCR (incrementing burst) type is requested. Any other value on these inputs is treated as an error condition and the Slave Illegal Burst (SIB) interrupt is asserted. In the case of a read request, the Bridge asserts SLVERR for all data beats and arbitrary data is placed on the s_axi_rdata bus. In the case of a write request, the Bridge asserts SLVERR for the write response and all write data is discarded.
+    * 
+* The normal operation of the Bridge core is dependent on the integrated block for PCIe establishing and maintaining the point-to-point link with an external device for PCIe. If the link has been lost, it must be re-established to return to normal operation.
+    * 
+* When a Hot Reset is received by the Bridge core, the link goes down and the PCI Configuration Space must be reconfigured.
+    * 
+* Initiated AXI4 write transactions that have not yet completed on the AXI4 bus when the link goes down have a SLVERR response given and the write data is discarded. Initiated AXI4 read transactions that have not yet completed on the AXI4 bus when the link goes down have a SLVERR response given, with arbitrary read data returned.
+    * 
+* Any MemWr TLPs for PCIe that have been received, but the associated AXI4 write transaction has not started when the link goes down, are discarded.
+    * 
+* Root Port BAR does not support packet filtering (all TLPs received from PCIe link are forwarded to the user logic), however Address Translation can be configured to enable or disable, depending on the IP configuration.
+    * 
+* During core customization in the Vivado® Design Suite, when there is no BAR enabled, RP passes all received packets to the user application without address translation or address filtering.
+    * 
+*  When BAR is enabled, by default the BAR address starts at 0x0000_0000 unless programmed separately. Any packet received from the PCIe® link that hits a BAR is translated according to the PCIE-to-AXI Address Translation rules.
+    *  The IP must not receive any TLPs outside of the PCIe BAR range from the PCIe link when RP BAR is enabled. If this rule cannot be enforced, it's recommended that the PCIe BAR is disabled and do address filtering and/or translation outside of the IP.
+* Endpoint mode only (parameter: set_finite_credit)
+    * FALSE: Infinite Completion credit is advertised to Root Complex.
+    * TRUE: Finite Completion credit is advertised to Root Complex.
+  .. warning::
+     PCIe specification requires Endpoint to advertise Infinite Completion credit only. Most Root Complex can obey Finite Completion credit advertisement from Endpoint, however use this option with caution.
+* AXI4-Lite Interfaces Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is valid and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive ensure that the following conditions are met. 
+    * For older versions of the AXI Bridge for PCIe Gen3 core with the axi_ctl_aclk port, ensure the axi_ctl_aclk and axi_ctl_aclk_out pins are connected to the design and are pulsing out of the IP.
+    * The interface is not being held in reset, and axi_aresetn is an active-Low reset. 
+    * Ensure that the main core clocks are toggling and that the enables are also asserted. 
+    * Has a simulation been run? Verify in simulation and/or a Vivado® Design Suite debug feature capture that the waveform is correct for accessing the AXI4-Lite interface.
+
+.. note::
+    The above debug gotchas are taken from QDMA Product Guide PG195.Please refer to the latest version of the document for new updates and more details. 
diff --git a/...rces/docs/DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/index.rst.txt b/...rces/docs/DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/index.rst.txt
@@ -0,0 +1,14 @@
+.. _bridge_pci_express:
+
+=========================================================
+DMA/Bridge Subsystem for PCI Express (Bridge IP Endpoint)
+=========================================================
+
+.. toctree::
+
+    debug_gotchas.rst
+    debug_faq.rst
+    issue_q&a_debug_tips.rst
+    links_docs_misc.rst
+    specific_issues.rst
+
diff --git a/...ridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/issue_q&a_debug_tips.rst.txt b/...ridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/issue_q&a_debug_tips.rst.txt
@@ -0,0 +1,18 @@
+.. .. _dma_bridge_ip_issues_answers:
+
+.. Issues and Answers
+.. ==================
+
+.. _dma_bridge_ip_issues_debug_tips_questions:
+
+Issues/Debug Tips/Questions
+===========================
+
+    * Relation between PCIe link up and axi_aresetn
+        * When the PCIe IP is in D0 uninitialized state which means it physically linked up but there hasn’t been any exchanges of INITFC and enumeration (Config TLPs) and thus no TLPs can get through. Only when axi_aresetn (which is essentially user_reset from PCIe IP) is released, that’s when the Transaction Layer is up. AXI peripherals should therefore use the axi_aresetn indication from the AXI Bridge IP before sending over a packet because this indicates when the Bridge and PCIe link is usable].
+    * Accessing the host testbench before the link is established results in the bridge IP to hang
+        * If the memory access is done after the link is established, it will return Slave Error or Decode error depending on whether it’s non-existent PCIe or AXI memory addresses. These type of errors should always get a response. When the memory access is attempted when there is no link, the system would hang as there is no response on the AXI bus as ready is not asserted without a link. In AXI, there is no Timeout mechanism by default unlike PCIe.  A possible workaround would be to use the firewall IP.
+    * The AXI outstanding number is set to be 8 (C_S_AXI_NUM_READ = 8), but only one AXI read can be issued instead of 8.
+        * Check by disabling "AXI Slave narow burst"
+    * The read access from the PCIe link reads the data equal to the size of the AXI bus width event though the read access is shorter than the AXI bus width
+        * This is a limitation in the IP. For PCIe® requests with lengths greater than 1 Dword, the size of the data burst on the MasterAXI interface will always equal the width of the AXI data bus even when the request received from the PCIe link is shorter than the AXI bus width. 
diff --git a/...DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/links_docs_misc.rst.txt b/...DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/links_docs_misc.rst.txt
@@ -0,0 +1,24 @@
+.. _dma_bridge_ip_docs_debug_collaterals:
+
+Documents and Debug Collaterals
+===============================
+
+.. csv-table::
+    :align: left
+    :file: csv/documents_and_debug_collaterlas.csv
+    :header-rows: 1
+
+.. _dma_bridge_ip_useful_links:
+
+Useful Links
+============
+
+.. csv-table::
+    :align: left
+    :file: csv/useful_links.csv
+    :header-rows: 1
+
+.. _dma_bridge_ip_misc:
+
+.. Miscellaneous
+.. =============
diff --git a/...DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/specific_issues.rst.txt b/...DMA_Bridge_Subsystem_for_PCI_Express_Bridge_IP_Endpoint/specific_issues.rst.txt
@@ -0,0 +1,18 @@
+.. _dma_bridge_ip_specific_issues:
+
+Specific Issues 
+================
+
+* Data trasfer issue
+    - Probe the M_AXI and S_AXI interfaces (depending on the direction of the data flow you are debugging) and see if you can trigger / catch the request you have made.
+    - If the packet shows up in here, check the address field (ARADDR for Read Request or AWADDR for Write Request) to ensure that the address is in the expected AXI Address (after translation) for this request.
+    - AXI Translation vector is at C_PCIEBAR2AXIBAR_# parameter and C_PCIEBAR2AXIBAR_# parameter. AXI BAR settings are at: C_AXIBAR_# parameter
+    - If the M_AXI and S_AXI interfaces do not show anything but this is not the first AXI packet prior to the failure, then check previous AXI transactions and make sure that they are completed.
+        - For Writes you must see a corresponding BRESP, BVALID, and BREADY for each request.
+        - For Reads you must see a corresponding RRESP, RVALID, and RREADY for each request.
+        - If there is any packet that is not completed (check both the Writes and Reads interface), investigate those first before moving forward, because PCIe has a strict packet ordering rule and that pending request might have halted the data pipeline.
+    - If the M_AXI and S_AXI interfaces do not show anything and this is the first AXI packet prior to the failure (or no other pending transaction), then check the following:
+        - The Bridge Enable bit in the Bridge Control Register (Offset 0x148 on s_axil_* AXI Lite interface) must be set to 1 before any data can flow through
+        - Check the AXIS_TX/RX interface and see if you can spot the packet there.
+        - If it is visible in the AXIS* interface, then the problem is in the Bridge.
+        - For AXI MM Gen2, internal state machines can be seen by following the AXIS_* signals datapath