test: enable gl tests

.github/workflows/gds.yaml

@@ -23,17 +23,79 @@ jobs:
   #    - name: Run Tiny Tapeout Precheck
   #      uses: TinyTapeout/tt-gds-action/precheck@tt09
 
-  #gl_test:
-  #  needs: gds
-  #  runs-on: ubuntu-24.04
-  #  steps:
-  #    - name: checkout repo
-  #      uses: actions/checkout@v4
-  #      with:
-  #        submodules: recursive
-  #
-  #    - name: GL test
-  #      uses: TinyTapeout/tt-gds-action/gl_test@tt09
+  gl_test:
+   needs: gds
+   runs-on: ubuntu-24.04
+   env: 
+      PDK_ROOT: ${{ github.workspace }}/IHP-Open-PDK
+      TEST_DIR: ${{ github.workspace }}/test
+   steps:
+     - name: checkout repo
+       uses: actions/checkout@v4
+       with:
+         submodules: recursive
+
+     - name: Download GDS artifact
+       uses: actions/download-artifact@v4
+       with:
+        name: tt_submission
+
+     - name: install PDK
+       uses: actions/checkout@v4
+       with:
+         repository: tinytapeout/IHP-Open-PDK
+         ref: tt
+         path: IHP-Open-PDK
+
+     - name: Setup python
+       uses: actions/setup-python@v5
+       with:
+         python-version: '3.11'
+
+     - name: Install Python packages
+       shell: bash
+       run: pip install -r test/requirements.txt
+
+     - name: Install iverilog
+       shell: bash
+       run: |
+          sudo apt-get update
+          sudo apt-get install -y bison flex gperf libbz2-dev
+          git clone https://github.com/steveicarus/iverilog
+          cd iverilog
+          git checkout d8c3c51ab1190ed3fb26540d7de6177f83e0e75b
+          sh autoconf.sh
+          ./configure
+          make
+          sudo make install
+
+     - name: Run tests
+       shell: bash
+       run: |
+         cp tt_submission/*.v "$TEST_DIR/gate_level_netlist.v"
+         cd "$TEST_DIR"
+         rm -f tb.vcd results.xml
+         make clean
+         GATES=yes make
+ 
+         # `make` will return success even if the tests fail, so check for failure in results.xml
+         test -f results.xml
+         ! grep failure results.xml
+
+     - name: Upload VCD
+       if: always()
+       uses: actions/upload-artifact@v4
+       with:
+           name: gatelevel_test_vcd
+           path: |
+             ${{ env.TEST_DIR }}/tb.vcd
+             ${{ env.TEST_DIR }}/results.xml
+
+     - name: Test Summary
+       if: always()
+       uses: test-summary/[email protected]
+       with:
+         paths: ${{ env.TEST_DIR }}/results.xml    
 
   viewer:
     needs: gds

test/Makefile

@@ -20,11 +20,9 @@ else
 SIM_BUILD				= sim_build/gl
 COMPILE_ARGS    += -DGL_TEST
 COMPILE_ARGS    += -DFUNCTIONAL
-COMPILE_ARGS    += -DUSE_POWER_PINS
 COMPILE_ARGS    += -DSIM
-COMPILE_ARGS    += -DUNIT_DELAY=\#1
-VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
-VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+VERILOG_SOURCES += $(PDK_ROOT)/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v
+VERILOG_SOURCES += $(PDK_ROOT)/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v
 
 # this gets copied in by the GDS action workflow
 VERILOG_SOURCES += $(PWD)/gate_level_netlist.v

test/tb.v

@@ -22,20 +22,9 @@ module tb ();
   wire [7:0] uo_out;
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
-`ifdef GL_TEST
-  wire VPWR = 1'b1;
-  wire VGND = 1'b0;
-`endif
 
   // Replace tt_um_example with your module name:
   tt_um_example user_project (
-
-      // Include power ports for the Gate Level test:
-`ifdef GL_TEST
-      .VPWR(VPWR),
-      .VGND(VGND),
-`endif
-
       .ui_in  (ui_in),    // Dedicated inputs
       .uo_out (uo_out),   // Dedicated outputs
       .uio_in (uio_in),   // IOs: Input path