Merge pull request #3 from htfab/main

Add fixes for openlane 2 warnings & openlane 2.1 errors
TinyTapeout · Sep 20, 2024 · 0dbde29 · 0dbde29
2 parents 60dc9b8 + 130263b
commit 0dbde29
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Showing 2 changed files with 12 additions and 12 deletions.
diff --git a/src/config.json b/src/config.json
@@ -11,17 +11,17 @@
 
   "//": "Here are some of the variables you may want to change:",
 
-  "//": "PL_TARGET_DENSITY - You can increase this if Global Placement fails with error GPL-0302.",
-  "//": "Users have reported that values up to 0.8 worked well for them.",
-  "PL_TARGET_DENSITY": 0.6,
+  "//": "PL_TARGET_DENSITY_PCT - You can increase this if Global Placement fails with error GPL-0302.",
+  "//": "Users have reported that values up to 80 worked well for them.",
+  "PL_TARGET_DENSITY_PCT": 60,
 
   "//": "CLOCK_PERIOD - Increase this in case you are getting setup time violations.",
   "//": "The value is in nanoseconds, so 20ns == 50MHz.",
   "CLOCK_PERIOD": 20,
 
   "//": "Hold slack margin - Increase them in case you are getting hold violations.",
   "PL_RESIZER_HOLD_SLACK_MARGIN": 0.1,
-  "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.05,
+  "GRT_RESIZER_HOLD_SLACK_MARGIN": 0.05,
 
   "//": "RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended!",
   "RUN_LINTER": 1,
@@ -42,10 +42,7 @@
   "RUN_KLAYOUT_DRC": 0,
 
   "//": "Don't put clock buffers on the outputs",
-  "PL_RESIZER_BUFFER_OUTPUT_PORTS": 0,
-
-  "//": "Allow use of specific sky130 cells",
-  "SYNTH_READ_BLACKBOX_LIB": 1,
+  "DESIGN_REPAIR_BUFFER_OUTPUT_PORTS": 0,
 
   "//": "Reduce wasted space",
   "TOP_MARGIN_MULT": 1,
@@ -56,7 +53,6 @@
   "//": "Absolute die size",
   "FP_SIZING": "absolute",
 
-  "PL_BASIC_PLACEMENT": 0,
   "GRT_ALLOW_CONGESTION": 1,
 
   "FP_IO_HLENGTH": 2,
@@ -77,7 +73,7 @@
   "RUN_CTS": 1,
 
   "//": "Don't use power rings or met5 layer",
-  "DESIGN_IS_CORE": 0,
+  "FP_PDN_MULTILAYER": 0,
   "RT_MAX_LAYER": "met4",
 
   "//": "MAGIC_DEF_LABELS may cause issues with LVS",

diff --git a/test/tb.v b/test/tb.v
@@ -22,14 +22,18 @@ module tb ();
   wire [7:0] uo_out;
   wire [7:0] uio_out;
   wire [7:0] uio_oe;
+`ifdef GL_TEST
+  wire VPWR = 1'b1;
+  wire VGND = 1'b0;
+`endif
 
   // Replace tt_um_example with your module name:
   tt_um_example user_project (
 
       // Include power ports for the Gate Level test:
 `ifdef GL_TEST
-      .VPWR(1'b1),
-      .VGND(1'b0),
+      .VPWR(VPWR),
+      .VGND(VGND),
 `endif
 
       .ui_in  (ui_in),    // Dedicated inputs