The-OpenROAD-Project · openroad-ci · Jan 6, 2026 · Jan 6, 2026 · Jan 7, 2026 · Jan 8, 2026
diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md
@@ -245,7 +245,7 @@ configuration file.
 | <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design. Non-existant modules are ignored silently, useful when listing modules statically, even if modules come and go dynamically.| |
 | <a name="SYNTH_CANONICALIZE_TCL"></a>SYNTH_CANONICALIZE_TCL| Specifies a Tcl script with commands to run as part of the synth canonicalize step.| |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| 0|
-| <a name="SYNTH_HDL_FRONTEND"></a>SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| |
+| <a name="SYNTH_HDL_FRONTEND"></a>SYNTH_HDL_FRONTEND| Select the language frontend to use for ingesting the design. Available options are: "slang" - SystemVerilog input by means of [slang](https://github.com/MikePopoloski/slang) and [yosys-slang](https://github.com/povik/yosys-slang) "yosys" - Verilog and limited SystemVerilog input by means of [internal Yosys support]](https://yosyshq.readthedocs.io/projects/yosys/en/0.40/cmd/read_verilog.html) "verific" - SystemVerilog input via a proprietary extension| slang|
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0|
 | <a name="SYNTH_HIER_SEPARATOR"></a>SYNTH_HIER_SEPARATOR| Separator used for the synthesis flatten stage.| .|
 | <a name="SYNTH_KEEP_MOCKED_MEMORIES"></a>SYNTH_KEEP_MOCKED_MEMORIES| When `SYNTH_MOCK_LARGE_MEMORIES=1`, setting this to 1, will keep mocked memories (not flattening them). This preserves some of the access logic complexity and avoids optimizations outside of the mocked memory.| 1|

diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json
@@ -12,7 +12,7 @@
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 10573,
+        "value": 19934,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 52923,
+        "value": 77305,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {

diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json
@@ -28,11 +28,11 @@
         "compare": "<="
     },
     "cts__timing__setup__ws": {
-        "value": -38.2,
+        "value": -69.5,
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -687.0,
+        "value": -1500.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -48,11 +48,11 @@
         "compare": "<="
     },
     "globalroute__timing__setup__ws": {
-        "value": -49.6,
+        "value": -72.6,
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -2160.0,
+        "value": -3090.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -1130.0,
+        "value": -1500.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

diff --git a/flow/designs/asap7/aes/config.mk b/flow/designs/asap7/aes/config.mk
@@ -29,3 +29,5 @@ else ifeq ($(FLOW_VARIANT),combine)
 	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v \
 	 $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v
 endif
+
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/asap7/ethmac/config.mk b/flow/designs/asap7/ethmac/config.mk
@@ -10,3 +10,5 @@ export CORE_UTILIZATION       = 70
 export CORE_ASPECT_RATIO      = 1
 export CORE_MARGIN            = 2
 export PLACE_DENSITY          = 0.75
+
+export SYNTH_HDL_FRONTEND     = yosys
diff --git a/flow/designs/asap7/ethmac_lvt/config.mk b/flow/designs/asap7/ethmac_lvt/config.mk
@@ -15,3 +15,5 @@ export PLACE_DENSITY          = 0.60
 export ASAP7_USE_VT           = LVT
 
 export RECOVER_POWER          = 1
+
+export SYNTH_HDL_FRONTEND     = yosys
diff --git a/flow/designs/asap7/gcd-ccs/rules-base.json b/flow/designs/asap7/gcd-ccs/rules-base.json
@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -103.0,
+        "value": -207.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -102.0,
+        "value": -187.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {

diff --git a/flow/designs/asap7/gcd/rules-base.json b/flow/designs/asap7/gcd/rules-base.json
@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -281.0,
+        "value": -422.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -439.0,
+        "value": -513.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -270.0,
+        "value": -361.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

diff --git a/flow/designs/asap7/mock-cpu/config.mk b/flow/designs/asap7/mock-cpu/config.mk
@@ -13,3 +13,5 @@ export PLACE_DENSITY            = 0.71
 export TNS_END_PERCENT          = 100
 
 export IO_CONSTRAINTS        = designs/asap7/mock-cpu/io.tcl
+
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/asap7/riscv32i/config.mk b/flow/designs/asap7/riscv32i/config.mk
@@ -29,3 +29,4 @@ export CTS_CLUSTER_DIAMETER = 50
 
 export SWAP_ARITH_OPERATORS = 1
 export OPENROAD_HIERARCHICAL = 1
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk
@@ -61,3 +61,4 @@ export ROUTING_LAYER_ADJUSTMENT = 0.2
 
 export SWAP_ARITH_OPERATORS = 1
 export OPENROAD_HIERARCHICAL = 1
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/aes/config.mk b/flow/designs/gf12/aes/config.mk
@@ -18,3 +18,4 @@ else
 export DESIGN_TYPE = CELL_NODEN
 endif
 
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk
@@ -34,3 +34,4 @@ export DESIGN_TYPE = CELL_NODEN
 endif
 
 export REMOVE_ABC_BUFFERS = 1
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/ariane133/config.mk b/flow/designs/gf12/ariane133/config.mk
@@ -31,3 +31,4 @@ export DESIGN_TYPE = CELL_NODEN
 endif
 
 export REMOVE_ABC_BUFFERS = 1
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/bp_dual/config.mk b/flow/designs/gf12/bp_dual/config.mk
@@ -66,3 +66,4 @@ export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
 export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
 
 export MACRO_PLACE_HALO = 7 7
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/bp_quad/config.mk b/flow/designs/gf12/bp_quad/config.mk
@@ -68,3 +68,4 @@ export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
 export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl
 
 export MACRO_PLACE_HALO = 7 7
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk
@@ -68,3 +68,4 @@ endif
 
 # enable slack margin for setup and hold fix after CTS
 export SETUP_SLACK_MARGIN ?= 100
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/coyote/config.mk b/flow/designs/gf12/coyote/config.mk
@@ -36,3 +36,5 @@ export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
 endif
+
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/gcd/config.mk b/flow/designs/gf12/gcd/config.mk
@@ -18,4 +18,4 @@ export DESIGN_TYPE = CELL_NODEN
 endif
 
 export SKIP_GATE_CLONING = 1
-
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/ibex/config.mk b/flow/designs/gf12/ibex/config.mk
@@ -27,3 +27,4 @@ endif
 # slack margin to address WC corner
 export SETUP_SLACK_MARGIN ?= 180
 export HOLD_SLACK_MARGIN ?= 50
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/jpeg/config.mk b/flow/designs/gf12/jpeg/config.mk
@@ -22,4 +22,4 @@ endif
 
 #export SKIP_PIN_SWAP     = 1
 export SKIP_GATE_CLONING = 1
-
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk
@@ -37,3 +37,4 @@ export DESIGN_TYPE = CELL_NODEN
 endif
 
 export REMOVE_ABC_BUFFERS = 1
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf12/tinyRocket/config.mk b/flow/designs/gf12/tinyRocket/config.mk
@@ -38,3 +38,5 @@ export DESIGN_TYPE = CELL
 else
 export DESIGN_TYPE = CELL_NODEN
 endif
+
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/gf180/aes-hybrid/rules-base.json b/flow/designs/gf180/aes-hybrid/rules-base.json
@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -144.0,
+        "value": -208.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -158.0,
+        "value": -230.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -154.0,
+        "value": -221.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

diff --git a/flow/designs/gf180/aes/rules-base.json b/flow/designs/gf180/aes/rules-base.json
@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -107.0,
+        "value": -141.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -124.0,
+        "value": -165.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -119.0,
+        "value": -157.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json
@@ -12,7 +12,7 @@
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 726,
+        "value": 1036,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 18889,
+        "value": 29243,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {

diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json
@@ -12,7 +12,7 @@
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 951,
+        "value": 1448,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 38152,
+        "value": 46152,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {

diff --git a/flow/designs/nangate45/ariane133/config.mk b/flow/designs/nangate45/ariane133/config.mk
@@ -27,3 +27,5 @@ export RTLMP_MAX_MACRO = 10
 export RTLMP_MIN_MACRO = 1
 export RTLMP_MAX_INST = 80000
 export RTLMP_MIN_INST = 8000
+
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/nangate45/ariane136/config.mk b/flow/designs/nangate45/ariane136/config.mk
@@ -22,3 +22,5 @@ export MACRO_PLACE_HALO = 10 10
 
 export TNS_END_PERCENT = 100
 export PLACE_DENSITY = 0.35
+
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/nangate45/black_parrot/config.mk b/flow/designs/nangate45/black_parrot/config.mk
@@ -38,3 +38,5 @@ export MACRO_PLACE_HALO    = 10 10
 export TNS_END_PERCENT     = 100
 
 export HOLD_SLACK_MARGIN = 0.03
+
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json
@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -12.8,
+        "value": -16.3,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -18.6,
+        "value": -19.9,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -17.1,
+        "value": -19.6,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -0.36,
+        "value": -0.753,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -0.795,
+        "value": -1.89,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

diff --git a/flow/designs/nangate45/bp_multi_top/config.mk b/flow/designs/nangate45/bp_multi_top/config.mk
@@ -35,3 +35,4 @@ export SKIP_GATE_CLONING      = 1
 
 export SWAP_ARITH_OPERATORS = 1
 export OPENROAD_HIERARCHICAL = 1
+export SYNTH_HDL_FRONTEND     = yosys
diff --git a/flow/designs/nangate45/gcd/rules-base.json b/flow/designs/nangate45/gcd/rules-base.json
@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 4515,
+        "value": 5793,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {

diff --git a/flow/designs/nangate45/jpeg/rules-base.json b/flow/designs/nangate45/jpeg/rules-base.json
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -41.1,
+        "value": -41.6,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

diff --git a/flow/designs/nangate45/swerv/config.mk b/flow/designs/nangate45/swerv/config.mk
@@ -11,3 +11,4 @@ export CORE_MARGIN = 5
 export PLACE_DENSITY_LB_ADDON = 0.25
 export TNS_END_PERCENT        = 100
 
+export SYNTH_HDL_FRONTEND = yosys
diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk
@@ -26,3 +26,4 @@ export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl
 
 export SWAP_ARITH_OPERATORS = 1
 export OPENROAD_HIERARCHICAL = 1
+export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -15,3 +15,5 @@ export PLACE_DENSITY = 0.60
		export ASAP7_USE_VT = LVT

		export RECOVER_POWER = 1

		export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -13,3 +13,5 @@ export PLACE_DENSITY = 0.71
		export TNS_END_PERCENT = 100

		export IO_CONSTRAINTS = designs/asap7/mock-cpu/io.tcl

		export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -29,3 +29,4 @@ export CTS_CLUSTER_DIAMETER = 50

		export SWAP_ARITH_OPERATORS = 1
		export OPENROAD_HIERARCHICAL = 1
		export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -61,3 +61,4 @@ export ROUTING_LAYER_ADJUSTMENT = 0.2

		export SWAP_ARITH_OPERATORS = 1
		export OPENROAD_HIERARCHICAL = 1
		export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -18,3 +18,4 @@ else
		export DESIGN_TYPE = CELL_NODEN
		endif

		export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -34,3 +34,4 @@ export DESIGN_TYPE = CELL_NODEN
		endif

		export REMOVE_ABC_BUFFERS = 1
		export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -31,3 +31,4 @@ export DESIGN_TYPE = CELL_NODEN
		endif

		export REMOVE_ABC_BUFFERS = 1
		export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -66,3 +66,4 @@ export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
		export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl

		export MACRO_PLACE_HALO = 7 7
		export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -68,3 +68,4 @@ export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl
		export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl

		export MACRO_PLACE_HALO = 7 7
		export SYNTH_HDL_FRONTEND = yosys
Original file line number	Diff line number	Diff line change
Expand Up		@@ -68,3 +68,4 @@ endif

		# enable slack margin for setup and hold fix after CTS
		export SETUP_SLACK_MARGIN ?= 100
		export SYNTH_HDL_FRONTEND = yosys