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Support latest PDK for September shuttle
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~ backported `wire rc` changes to superstable version so it can work with later PDKs
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donn committed Sep 5, 2024
1 parent 30ee138 commit f36250a
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2 changes: 1 addition & 1 deletion README.md
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Expand Up @@ -24,7 +24,7 @@ The short version is, to install the OpenLane environment...
1. [Get Docker](https://docs.docker.com/get-docker/) (or a compatible container engine)
* On Ubuntu, follow the [Docker post install instructions](https://docs.docker.com/engine/install/linux-postinstall/) after you install Docker.
2. Get Python 3.6 or higher ([macOS](https://formulae.brew.sh/formula/python3) | [Ubuntu](https://packages.ubuntu.com/focal/python3))
2. Get a version between Python 3.6 and Python 3.10: ([macOS](https://formulae.brew.sh/formula/python3) | [Ubuntu](https://packages.ubuntu.com/focal/python3))
* On Ubuntu, you may also need to install venv: `apt-get install python3-venv`, and pip: `apt-get install python3-pip`.
3. Get git ([macOS](https://formulae.brew.sh/formula/git) | [Ubuntu](https://packages.ubuntu.com/focal/git))
4. Get GNU Make ([macOS](https://formulae.brew.sh/formula/make) | [Ubuntu](https://packages.ubuntu.com/focal/make))
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2 changes: 1 addition & 1 deletion dependencies/tool_metadata.yml
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Expand Up @@ -73,6 +73,6 @@
in_install: false
- name: open_pdks
repo: https://github.com/RTimothyEdwards/open_pdks
commit: 78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc
commit: 0fe599b2afb6708d281543108caf8310912f54af
in_install: false
pdk: true
4 changes: 3 additions & 1 deletion docs/source/reference/pdk_configuration.md
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Expand Up @@ -63,13 +63,15 @@ you're doing.
| `GPIO_PADS_PREFIX` | A list of pad cells name prefixes. |
| `NETGEN_SETUP_FILE` | Points to the setup file for netgen(lvs), that can exclude certain cells etc.. |
| `FP_TAPCELL_DIST` | The distance between tapcell columns. Used in floorplanning in tapcell insertion. |
| `WIRE_RC_LAYER` | The metal layer used in estimate parastics `set_wire_rc`. <br> (Example: `met1`) |
| `DATA_WIRE_RC_LAYER` | The metal layer used in estimate parastics `set_wire_rc`. <br> (Example: `met2`) |
| `CLOCK_WIRE_RC_LAYER` | The metal layer used in estimate parastics `set_wire_rc`. <br> (Example: `met5`) |
| `FP_IO_HLAYER` | The metal layer on which to place the io pins horizontally (top and bottom of the die). <br>(Example: `met3`)|
| `FP_IO_VLAYER` | The metal layer on which to place the io pins vertically (sides of the die) <br> (Example: `met2`)|
| `FP_TAPCELL_DIST` | The horizontal distance between two tapcell columns <br> (Default: `14`) |
| `RCX_RULES_MIN` | OpenRCX rules at the minimum corner. (Optional) |
| `RCX_RULES` | OpenRCX rules at the nominal corner. |
| `RCX_RULES_MAX` | OpenRCX rules at the maximum corner. (Optional) |
| `WIRE_RC_LAYER` | **Deprecated: Use `DATA_WIRE_RC_LAYER` and `CLOCK_WIRE_RC_LAYER`** The metal layer used in estimate parastics `set_wire_rc`. |

## SCL-specific variables

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8 changes: 5 additions & 3 deletions scripts/openroad/common/set_rc.tcl
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Expand Up @@ -35,7 +35,9 @@ if { [info exist ::env(LAYERS_RC)] } {
}
}

if { [info exist ::env(WIRE_RC_LAYER)] } {
set_wire_rc -signal -layer $::env(WIRE_RC_LAYER)
set_wire_rc -clock -layer $::env(WIRE_RC_LAYER)
if { [info exist ::env(DATA_WIRE_RC_LAYER)] } {
set_wire_rc -signal -layer $::env(DATA_WIRE_RC_LAYER)
}
if { [info exist ::env(CLOCK_WIRE_RC_LAYER)] } {
set_wire_rc -clock -layer $::env(CLOCK_WIRE_RC_LAYER)
}
1 change: 1 addition & 0 deletions scripts/tcl_commands/all.tcl
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Expand Up @@ -621,6 +621,7 @@ proc prep {args} {
handle_deprecated_pdk_config SYNTH_MAX_TRAN MAX_TRANSITION_CONSTRAINT
handle_deprecated_pdk_config SYNTH_MAX_FANOUT MAX_FANOUT_CONSTRAINT
handle_deprecated_pdk_config SYNTH_CAP_LOAD OUTPUT_CAP_LOAD
handle_deprecated_pdk_config WIRE_RC_LAYER DATA_WIRE_RC_LAYER

## Flow
handle_diode_insertion_strategy
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