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Overhaul Linter Handling of Black-boxed Verilog Models (#1929)
+ add `generate_blackbox_verilog` that generates a black-boxed header file from a list of Verilog models + add `scripts/synth/blackbox.tcl` for `generate_blackbox_verilog` + use `generate_blackbox_verilog` with `VERILOG_FILES_BLACKBOX` and PDK verilog models + disable `UNDRIVEN` and `UNUSEDSIGNAL` for PDK verilog files + add `YOSYS_IN`, `YOSYS_OUT`, `YOSYS_DEFINES` which are used in blackbox.tcl to internal variables in ci variables documentation workflow ~ enable `LINTER_INCLUDE_PDK_MODELS` Co-authored-by: Donn <[email protected]>
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Submodule ci
updated
3 files
| +4 −1 | APU/config.json | |
| +5 −9 | test_sram_macro/config.json | |
| +48 −51 | test_sram_macro/src/test_sram_macro.v |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,49 @@ | ||
| # Copyright 2023 Efabless Corporation | ||
| # | ||
| # Licensed under the Apache License, Version 2.0 (the "License"); | ||
| # you may not use this file except in compliance with the License. | ||
| # You may obtain a copy of the License at | ||
| # | ||
| # http://www.apache.org/licenses/LICENSE-2.0 | ||
| # | ||
| # Unless required by applicable law or agreed to in writing, software | ||
| # distributed under the License is distributed on an "AS IS" BASIS, | ||
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| # See the License for the specific language governing permissions and | ||
| # limitations under the License. | ||
| import re | ||
| import click | ||
| from enum import Enum | ||
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| @click.command() | ||
| @click.option("-o", "--output", default=None) | ||
| @click.argument( | ||
| "file_in", | ||
| type=click.Path(exists=True, file_okay=True, dir_okay=False), | ||
| required=True, | ||
| ) | ||
| def clean_models(output, file_in): | ||
| class State(Enum): | ||
| output = 0 | ||
| primitive = 1 | ||
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| out_file = None | ||
| if output is not None: | ||
| out_file = open(output, "w", encoding="utf8") | ||
| bad_yosys_line = re.compile(r"^\s+\S+\s*\(.*\).*;") | ||
| state = State.output | ||
| for line in open(file_in, "r", encoding="utf8"): | ||
| if state == State.output: | ||
| if line.strip().startswith("primitive"): | ||
| state = State.primitive | ||
| elif bad_yosys_line.search(line) is None: | ||
| print(line.strip("\n"), file=out_file) | ||
| elif state == State.primitive: | ||
| if line.strip().startswith("endprimitive"): | ||
| print("/* removed primitive */", file=out_file) | ||
| state = State.output | ||
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| if __name__ == "__main__": | ||
| clean_models() |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,24 @@ | ||
| # Copyright 2023 Efabless Corporation | ||
| # | ||
| # Licensed under the Apache License, Version 2.0 (the "License"); | ||
| # you may not use this file except in compliance with the License. | ||
| # You may obtain a copy of the License at | ||
| # | ||
| # http://www.apache.org/licenses/LICENSE-2.0 | ||
| # | ||
| # Unless required by applicable law or agreed to in writing, software | ||
| # distributed under the License is distributed on an "AS IS" BASIS, | ||
| # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| # See the License for the specific language governing permissions and | ||
| # limitations under the License. | ||
|
|
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| yosys -import | ||
| foreach input $::env(YOSYS_IN) { | ||
| if { [info exists ::env(YOSYS_DEFINES)] } { | ||
| read_verilog -lib -D$::env(YOSYS_DEFINES) $input | ||
| } else { | ||
| read_verilog -lib $input | ||
| } | ||
| } | ||
| blackbox * | ||
| write_verilog -noattr -noexpr -nohex -nodec -defparam -blackboxes $::env(YOSYS_OUT) |