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SPI+DMA enablements #11

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b8e58f7
am261x: boards/soc/dts: clean up
MihiraMadhava Dec 22, 2025
d077e44
drivers: dma: fix compiler warnings in dma_ti_edma
MihiraMadhava Dec 25, 2025
15c0713
drivers: serial: ns16550 fix enable_dma_fifo
MihiraMadhava Dec 22, 2025
26ea58a
dma: ti_edma: Parameterize M2P manual trigger
Shreyas-Shankar155 Dec 24, 2025
c1e68ff
soc: am261x: Add UART-eDMA support
Shreyas-Shankar155 Dec 25, 2025
1257f6f
drivers: spi: Add DMA support to OMAP McSPI
Shreyas-Shankar155 Dec 24, 2025
d8ca7d8
soc: am261x: Adding McSPI Support
Shreyas-Shankar155 Dec 24, 2025
a244330
dts: am261x: Add McSPI
Shreyas-Shankar155 Dec 24, 2025
6fdb944
boards: am261x_lp: Add McSPI2
Shreyas-Shankar155 Dec 24, 2025
20b8f2a
docs: am261x_lp: Add McSPI DMA integration
Shreyas-Shankar155 Dec 25, 2025
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9 changes: 0 additions & 9 deletions boards/ti/am261x_lp/Kconfig
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This file was deleted.

18 changes: 2 additions & 16 deletions boards/ti/am261x_lp/Kconfig.am261x_lp
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Original file line number Diff line number Diff line change
Expand Up @@ -5,19 +5,5 @@
# SPDX-License-Identifier: Apache-2.0

config BOARD_AM261X_LP
bool "Board AM261X LP Selecting"
select SOC_SERIES_AM261X_R5F

config BOARD_AM261X_LP_AM2612_R5F0_0
bool "TI AM261X LaunchPad For Core R5F0_0"
select BOARD_AM261X_LP
select SOC_AM261X_R5F0_0
help
Build for TI AM261X LaunchPad with R5F Core 0

config BOARD_AM261X_LP_AM2612_R5F0_1
bool "TI AM261X LaunchPad For Core R5F0_1"
select BOARD_AM261X_LP
select SOC_AM261X_R5F0_1
help
Build for TI AM261X LaunchPad with R5F Core 1
select SOC_AM261X_R5F0_0 if BOARD_AM261X_LP_AM2612_R5F0_0
select SOC_AM261X_R5F0_1 if BOARD_AM261X_LP_AM2612_R5F0_1
19 changes: 10 additions & 9 deletions boards/ti/am261x_lp/am261x_lp_am2612_r5f0_0.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/

/dts-v1/;

#include <ti/am26x/am261x_r5f0_0.dtsi>
#include <zephyr/dt-bindings/pinctrl/ti-am26x-pinctrl.h>
#include <zephyr/dt-bindings/dma/ti_edma.h>
Expand All @@ -29,6 +27,7 @@

leds {
compatible = "gpio-leds";

led0: led_0 {
/* gpio 84 is in bank 5, so 20th pin in the bank4-5 set */
gpios = <&gpio0_bank_4_5 20 1>;
Expand All @@ -38,10 +37,11 @@

buttons {
compatible = "gpio-keys";

user_button: button_0 {
/* Replace with the correct GPIO pin for your button */
gpios = <&gpio0_bank_6_7 28 1>;
label = "User Button";
/* Replace with the correct GPIO pin for your button */
gpios = <&gpio0_bank_6_7 28 1>;
label = "User Button";
};
};
};
Expand Down Expand Up @@ -77,24 +77,26 @@
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(129),
(PIN_MODE(0) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_0))>;
};

spi2_d0: spi2_d0 {
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(130),
(PIN_MODE(0) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_0))>;
};

spi2_d1: spi2_d1 {
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(128),
(PIN_MODE(0) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_0))>;
};

spi2_cs0: spi2_cs0 {
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(138),
(PIN_MODE(4) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_0))>;
};

spi2_cs1: spi2_cs1 {
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(126),
(PIN_MODE(2) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_0))>;
};


};

&uart0 {
Expand All @@ -107,6 +109,7 @@

&gpio0_bank_4_5 {
status = "okay";

mux-hog {
gpio-hog;
gpios = <20 1>;
Expand All @@ -126,13 +129,11 @@
status = "okay";
region-id = <0>;
queue-number = <0>;

edma-resources = <RESOURCE_TYPE_DMA_CHANNEL 0 31>,
<RESOURCE_TYPE_PARAM 0 127 >;
};

&mcspi2 {
pinctrl-0 = <&spi2_clk &spi2_cs0 &spi2_d0 &spi2_d1>;
pinctrl-names = "default";
status = "okay";
};
18 changes: 10 additions & 8 deletions boards/ti/am261x_lp/am261x_lp_am2612_r5f0_1.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/

/dts-v1/;

#include <ti/am26x/am261x_r5f0_1.dtsi>
#include <zephyr/dt-bindings/pinctrl/ti-am26x-pinctrl.h>
#include <zephyr/dt-bindings/dma/ti_edma.h>
Expand All @@ -29,6 +27,7 @@

leds {
compatible = "gpio-leds";

led0: led_0 {
/* gpio 84 is in bank 5, so 20th pin in the bank4-5 set */
gpios = <&gpio1_bank_4_5 20 1>;
Expand All @@ -38,10 +37,11 @@

buttons {
compatible = "gpio-keys";

user_button: button_0 {
/* Replace with the correct GPIO pin for your button */
gpios = <&gpio1_bank_6_7 28 1>;
label = "User Button";
/* Replace with the correct GPIO pin for your button */
gpios = <&gpio1_bank_6_7 28 1>;
label = "User Button";
};
};
};
Expand Down Expand Up @@ -77,23 +77,26 @@
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(129),
(PIN_MODE(0) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_1))>;
};

spi2_d0: spi2_d0 {
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(130),
(PIN_MODE(0) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_1))>;
};

spi2_d1: spi2_d1 {
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(128),
(PIN_MODE(0) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_1))>;
};

spi2_cs0: spi2_cs0 {
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(138),
(PIN_MODE(4) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_1))>;
};

spi2_cs1: spi2_cs1 {
pinmux = <TI_AM26X_PINMUX(PIN_GPIO(126),
(PIN_MODE(2) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_GPIO_R5SS0_1))>;
};

};

&uart0 {
Expand All @@ -106,6 +109,7 @@

&gpio1_bank_4_5 {
status = "okay";

mux-hog {
gpio-hog;
gpios = <20 1>;
Expand All @@ -125,13 +129,11 @@
status = "okay";
region-id = <1>;
queue-number = <0>;

edma-resources = <RESOURCE_TYPE_DMA_CHANNEL 32 63>,
<RESOURCE_TYPE_PARAM 128 255 >;
};

&mcspi2 {
pinctrl-0 = <&spi2_clk &spi2_cs0 &spi2_d0 &spi2_d1>;
pinctrl-names = "default";
status = "okay";
};
10 changes: 10 additions & 0 deletions boards/ti/am261x_lp/doc/index.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,8 @@ In AM261x, each McSPI supports up to 2 CS lines.

However, the McSPI driver currently supports only single-channel transfer per McSPI interface.

**NOTE:Only Channel 0 of any McSPI has default DMA support.**

|

Data Movement Architecture
Expand Down Expand Up @@ -148,6 +150,14 @@ Some IPs also have DMA channels configured by default:
+----------+--------------+--------------+
| UART5 | Tx:11 Rx:12 | Tx: 43 Rx: 44|
+----------+--------------+--------------+
| McSPI0 | Tx:13 Rx:14 | Tx: 45 Rx: 46|
+----------+--------------+--------------+
| McSPI1 | Tx:15 Rx:16 | Tx: 47 Rx: 48|
+----------+--------------+--------------+
| McSPI2 | Tx:17 Rx:18 | Tx: 49 Rx: 50|
+----------+--------------+--------------+
| McSPI3 | Tx:19 Rx:20 | Tx: 51 Rx: 52|
+----------+--------------+--------------+

|

Expand Down
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