Implement FlexConnect and add tests (VPAC VISS+MSC) GStreamer plugin by PrathamTI · Pull Request #378 · TexasInstruments/edgeai-gst-plugins

PrathamTI · 2025-12-24T11:43:03Z

Implement FlexConnect hardware-accelerated ISP pipeline combining VISS and MSC in a single
GStreamer element for TI AM62A and compatible platforms.

This implementation is based on the official TI FlexConnect kernel node enabled in TI Processor
SDK RTOS[0].

Current Implementation:

Single output stream support - FlexConnect can take raw Bayer camera input and produce one processed output stream (e.g., 1920x1080 NV12 or GRAY8)
Two output formats supported - NV12: Standard color format (YUV 4:2:0) for display/encode - GRAY8: 8-bit grayscale for computer vision applications
Mutliple camera suppor - Flexconnect is supported on multiple camera (e.g IMX219, IMX390, etc)

Test Suite:
Comprehensive test suite added for FlexConnect plugin validation:

test_target
- Validates target property with supported values (VPAC_FC)
test_foreach_format
- Tests all supported Bayer input formats (bggr, gbrg, grbg, rggb)
- Validates format conversion to NV12 output
test_resolutions_with_downscale_fail
- Validates FC correctly rejects downscaling attempts
- Tests hardware limitation (output must be >= input dimensions)
test_resolutions_with_upscale_fail
- Validates FC correctly rejects odd output dimensions
- Tests NV12 format constraint (requires even width/height)
test_input_format_fail
- Tests invalid Bayer input format rejection
- Validates caps negotiation failure during state change
test_output_format_fail
- Tests invalid output format rejection for all valid input formats
- Validates proper format validation behavior

TODO:

Multiple output stream support
Add support for TIVX_VPAC_FC_MSC_CMD_SET_CROP_PARAMS control command.

[0] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/tiovx/docs/user_guide/hwa__vpac__fc_8h_source.html

cshilwant · 2025-12-24T11:48:13Z

@PrathamTI For SITSW-8156, are you planning to add tests for this new plugin via [0]?

[0] - https://github.com/TexasInstruments/edgeai-gst-plugins/tree/main/tests/check

cshilwant · 2025-12-24T11:52:16Z

In commit message,

Mutliple camera suppor --> 3. Mutliple camera support

PrathamTI · 2025-12-24T12:00:20Z

@PrathamTI For SITSW-8156, are you planning to add tests for this new plugin via [0]?

[0] - https://github.com/TexasInstruments/edgeai-gst-plugins/tree/main/tests/check

Yes, planning on adding tests after the bug is resolved

cshilwant · 2025-12-24T12:15:54Z

Yes, planning on adding tests after the bug is resolved

@PrathamTI Bisecting the color artifacts issue in imaging and resolving the crop params control command bug might take some time.

However, I noticed that the tests under edgeai-gst-plugins/tests/check use fakesink, which actually unblocks us for adding tests...since the color artifacts we're observing are specific to kmssink. Given this, the bug shouldn't block us from adding tests under edgeai-gst-plugins/tree/main/tests/check & close SITSW-8156

Adding unit tests for tiovxfcvissmsc now would help us validate the pipeline behavior for each RC through automation. Without these tests in place, we'd need to perform manual validation for every RC going forward (something we can avoid by adding automated unit tests now)

If you don't have the implementation ready yet, you can check out gsttiovxisp.c to get started. We should also evaluate how many positive and negative tests from tiovxisp can be reused for tiovxfcvissmsc and then identify what additional tests specific to tiovxfcvissmsc need to be added.

PrathamTI · 2025-12-26T05:16:29Z

Yes, planning on adding tests after the bug is resolved

@PrathamTI Bisecting the color artifacts issue in imaging and resolving the crop params control command bug might take some time.

However, I noticed that the tests under edgeai-gst-plugins/tests/check use fakesink, which actually unblocks us for adding tests...since the color artifacts we're observing are specific to kmssink. Given this, the bug shouldn't block us from adding tests under edgeai-gst-plugins/tree/main/tests/check & close SITSW-8156

Adding unit tests for tiovxfcvissmsc now would help us validate the pipeline behavior for each RC through automation. Without these tests in place, we'd need to perform manual validation for every RC going forward (something we can avoid by adding automated unit tests now)

If you don't have the implementation ready yet, you can check out gsttiovxisp.c to get started. We should also evaluate how many positive and negative tests from tiovxisp can be reused for tiovxfcvissmsc and then identify what additional tests specific to tiovxfcvissmsc need to be added.

Good Idea
I'll work on this after this sprint

v-singh1 · 2026-01-13T10:09:45Z

ext/tiovx/gsttiovxfc.c

@@ -0,0 +1,2716 @@
+/*
+ * Copyright (c) [2025] Texas Instruments Incorporated


Update copyright year

v-singh1 · 2026-01-13T10:25:15Z

ext/tiovx/gsttiovxfc.c

+{
+  GstTIOVXFC *self = NULL;
+  vx_status status = VX_FAILURE;
+  gboolean ret = FALSE;


do you really need ret, can you use status ?

v-singh1 · 2026-01-13T10:26:02Z

ext/tiovx/gsttiovxfc.c

+gst_tivox_fc_compute_src_dimension (GstTIOVXSimo * simo,
+    const GValue * dimension, GValue * out_value, guint roi_len)
+{
+  static const gint scale = 4;


what is 4, better to use #define or add comment

v-singh1 · 2026-01-13T10:26:50Z

ext/tiovx/gsttiovxfc.c

+  }
+
+  out_max = dim_max;
+  out_min = 1.0 * dim_min / scale + 0.5;


again here, 0.5, 1.0 ?
add some comments

v-singh1 · 2026-01-13T10:27:15Z

ext/tiovx/gsttiovxfc.c

+gst_tivox_fc_compute_sink_dimension (GstTIOVXSimo * simo,
+    const GValue * dimension, GValue * out_value, guint roi_len)
+{
+  static const gint scale = 4;


v-singh1 · 2026-01-13T10:40:36Z

ext/tiovx/gsttiovxfc.c

+          }
+          else
+          {
+


v-singh1 · 2026-01-13T10:41:29Z

ext/tiovx/gsttiovxfc.c

+              GST_ERROR_OBJECT (self, "Unable to call analog gain ioctl: %d",
+                ret_val);
+          }
+          close_fd:


v-singh1 · 2026-01-13T10:46:14Z

ext/tiovx/gsttiovxfc.c

+    GST_DEBUG_OBJECT (self, "Configuring IR/Bayer operation based on output format");
+
+    /* Detect if input is Bayer format for GRAY8 output decision */
+    is_bayer_input = FALSE;


it is already initialize as FALSE, why again ?

v-singh1 · 2026-01-13T10:47:42Z

ext/tiovx/gsttiovxfc.c

+
+        /* Configure MSC outputs - route IR output to MSC output 0 */
+        GST_DEBUG_OBJECT (self, "Configuring MSC outputs for IR");
+        for (int i = 6; i <= 10; i++) {


6/10 ? add comment

v-singh1 · 2026-01-13T10:49:01Z

ext/tiovx/gsttiovxfc.c

+    GST_DEBUG_OBJECT (self, "Module init succeeded");
+    ret = TRUE;
+
+out:    


cleanup of resources ?

Akshay-Abdar · 2026-01-13T11:07:36Z

ext/tiovx/gsttiovxfc.h

+ *
+ * DISCLAIMER.
+ *
+ * THIS SOFTWARE IS PROVItivx_vpac_fc_viss_msc_params_tDED BY TI AND TI’S LICENSORS "AS IS" AND ANY EXPRESS


tivx_vpac_fc_viss_msc_params_t is i guess mistakenly pasted here. Correct the same

Akshay-Abdar · 2026-01-13T11:28:34Z

Update the copyright year from [2022-2026] is the year range i suppose for the file ext/tiovx/gsttiovx.c as there are few updates.

sinha-shreyash · 2026-01-14T13:22:42Z

ext/tiovx/gsttiovxfc.c

+    }
+
+    GST_DEBUG_OBJECT(self, "Setting up VISS-MSC input mapping");
+    flexconnect->fc_params.msc_in_thread_viss_out_map[0] = TIVX_VPAC_FC_VISS_OUT2;


any reason behind not using TIVX_VPAC_FC_VISS_OUT0/1 ?

As defined in [0], for VPAC3 or VPAC3L devices msc_in_thread_viss_out_map should be mapped to TIVX_VPAC_FC_VISS_OUT2.

[0] https://git.ti.com/cgit/processor-sdk/imaging/tree/kernels/hwa/test/test_vpac_fc.c?h=safety_next#n345

In https://bitbucket.itg.ti.com/projects/PROCESSOR-SDK-VISION/repos/edgeai-tiovx-modules/pull-requests/69/diff#src%2Ftiovx_fc_module.c?t=88, you have mapped msc_in_thread_viss_out_map to TIVX_VPAC_FC_VISS_OUT0 and 1 and rest to invalid. Is it a delta or is there any reason behind this ?

For TIOVX module params initialisation, Imaging kernel has enabled TIVX_VPAC_FC_VISS_OUT0 and TIVX_VPAC_FC_VISS_OUT1 [0] so followed the same in tiovx_fc_module.c and the gstreamer implementation was based on [1] test case so the mapping of TIVX_VPAC_FC_VISS_OUT2 and TIVX_VPAC_FC_VISS_OUT3 was required.

[0] https://git.ti.com/cgit/processor-sdk/imaging/tree/kernels/hwa/host/vx_vpac_fc_host.c?h=REL.PSDK.ANALYTICS.11.02.00.06#n1108

[1] https://git.ti.com/cgit/processor-sdk/imaging/tree/kernels/hwa/test/test_vpac_fc.c?h=safety_next#n221

v-singh1 · 2026-01-30T04:08:01Z

ext/tiovx/gsttiovxfc.h

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) [2025] Texas Instruments Incorporated


change copyright year

v-singh1

change copyright year in ext/tiovx/gsttiovxfc.h

Implement FlexConnect hardware-accelerated ISP pipeline combining VISS and MSC in a single GStreamer element for TI AM62A and compatible platforms. This implementation is based on the official TI FlexConnect kernel node enabled in TI Processor SDK RTOS[0]. Current Implementation: 1. Single output stream support - FlexConnect can take raw Bayer camera input and produce one processed output stream (e.g., 1920x1080 NV12 or GRAY8) 2. Two output formats supported - NV12: Standard color format (YUV 4:2:0) for display/encode - GRAY8: 8-bit grayscale for computer vision applications 3. Mutliple camera support - Flexconnect is supported on multiple camera (e.g IMX219, IMX390, etc) Test Suite: Comprehensive test suite added for FlexConnect plugin validation: 1. test_target - Validates target property with supported values (VPAC_FC) 2. test_foreach_format - Tests all supported Bayer input formats (bggr, gbrg, grbg, rggb) - Validates format conversion to NV12 output 3. test_resolutions_with_downscale_fail - Validates FC correctly rejects downscaling attempts - Tests hardware limitation (output must be >= input dimensions) 4. test_resolutions_with_upscale_fail - Validates FC correctly rejects odd output dimensions - Tests NV12 format constraint (requires even width/height) 5. test_input_format_fail - Tests invalid Bayer input format rejection - Validates caps negotiation failure during state change 6. test_output_format_fail - Tests invalid output format rejection for all valid input formats - Validates proper format validation behavior TODO: 1. Multiple output stream support 2. Add support for TIVX_VPAC_FC_MSC_CMD_SET_CROP_PARAMS control command. [0] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/tiovx/docs/user_guide/hwa__vpac__fc_8h_source.html Signed-off-by: Pratham Deshmukh <p-deshmukh@ti.com>

PrathamTI requested review from Akshay-Abdar, cshilwant and v-singh1 December 24, 2025 11:44

PrathamTI changed the base branch from main to develop December 24, 2025 11:48

PrathamTI force-pushed the flexconnect branch from 0b2278a to 7478a40 Compare December 24, 2025 11:58

PrathamTI force-pushed the flexconnect branch from 7478a40 to a47b754 Compare January 13, 2026 09:23

PrathamTI changed the title ~~Implement FlexConnect (VPAC VISS+MSC) GStreamer plugin~~ Implement FlexConnect and add tests (VPAC VISS+MSC) GStreamer plugin Jan 13, 2026

PrathamTI marked this pull request as ready for review January 13, 2026 09:45

cshilwant requested a review from sinha-shreyash January 13, 2026 09:57

v-singh1 suggested changes Jan 13, 2026

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Akshay-Abdar reviewed Jan 13, 2026

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sinha-shreyash reviewed Jan 14, 2026

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PrathamTI force-pushed the flexconnect branch from 0952ec7 to a647124 Compare January 22, 2026 14:07

PrathamTI requested review from Akshay-Abdar, sinha-shreyash and v-singh1 January 22, 2026 14:22

v-singh1 reviewed Jan 30, 2026

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ext/tiovx/gsttiovxfc.h Outdated

@@ -0,0 +1,88 @@

/*

* Copyright (c) [2025] Texas Instruments Incorporated

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change copyright year

v-singh1 reviewed Jan 30, 2026

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PrathamTI force-pushed the flexconnect branch from a647124 to 779d466 Compare February 2, 2026 09:53

PrathamTI requested a review from v-singh1 February 2, 2026 09:58

		@@ -0,0 +1,2716 @@
		/*
		* Copyright (c) [2025] Texas Instruments Incorporated

		@@ -0,0 +1,88 @@
		/*
		* Copyright (c) [2025] Texas Instruments Incorporated

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