Clock

on TWRP

~ # cat /proc/clkmgr/clk_force_on
********** clk force on info dump **********

********** clk_force_on help **********
set clk force on: echo set id > /proc/clkmgr/clk_force_on
clr clk force on: echo clr id > /proc/clkmgr/clk_force_on
~ #

~ # cat /proc/clkmgr/clk_test
********** clk register dump **********
[00][CG_PERI0]=[0xffafebfd]
[01][CG_PERI1]=[0x00000009]
[02][CG_INFRA]=[0x00008040]
[03][CG_TOPCK]=[0x00000000]
[04][CG_DISP0]=[0xffff1e8e]
[05][CG_DISP1]=[0xffffffc7]
[06][CG_IMAGE]=[0x00000000]
[07][CG_MFG  ]=[0x00000000]
[08][CG_AUDIO]=[0x80394078]
[09][CG_VDEC0]=[0x00000000][0x00000000]
[10][CG_VDEC1]=[0x00000000][0x00000000]
[11][CG_VENC ]=[0x00000000]
[PERI_PDN_MD_MASK]=0x00000001
[PERI_PDN0_MD1_STA]=0x00000000
[PERI_PDN0_MD2_STA]=0xffffffff

********** clk_test help **********
enable  clk: echo enable  id [mod_name] > /proc/clkmgr/clk_test
disable clk: echo disable id [mod_name] > /proc/clkmgr/clk_test
read state:  echo id > /proc/clkmgr/clk_test
~ #

~ # cat /proc/clkmgr/mux_test
********** mux register dump **********
[CLK_CFG_0]=0x82870305
[CLK_CFG_1]=0x04820281
[CLK_CFG_2]=0x85858585
[CLK_CFG_3]=0x80808001
[CLK_CFG_4]=0x01848687
[CLK_CFG_5]=0x000003ff
[CLK_CFG_6]=0x00818101
[CLK_CFG_7]=0x01018101
[CLK_MISC_CFG_2]=0x00000011
[CLK_CFG_8]=0x00818505

********** mux_test help **********
~ #

~ # cat /proc/clkmgr/pll_fsel
[0][ARMPLL ]=[0x80000001800ba000]
[1][MAINPLL]=[-1]
[2][MSDCPLL]=[-1]
[3][TVDPLL ]=[-1]
[4][LVDSPLL]=[-1]
[5][UNIVPLL]=[0xfb003001]
[6][MMPLL  ]=[-1]
[7][ISPPLL ]=[-1]

********** pll_fsel help **********
adjust pll frequency:  echo id freq > /proc/clkmgr/pll_fsel
~ #

~ # cat /proc/clkmgr/pll_test
********** pll register dump **********
[0][ARMPLL  reg0]=[0x80000001]
[0][ARMPLL  reg1]=[0x800ba000]
[0][ARMPLL  reg2]=[0x80000001]
[1][MAINPLL reg0]=[0xf0000000]
[1][MAINPLL reg1]=[0x000f8000]
[1][MAINPLL reg2]=[0x00000002]
[2][MSDCPLL reg0]=[0x80000080]
[2][MSDCPLL reg1]=[0x000f0000]
[2][MSDCPLL reg2]=[0x00000002]
[3][TVDPLL  reg0]=[0x80000080]
[3][TVDPLL  reg1]=[0x800b6c4f]
[3][TVDPLL  reg2]=[0x00000002]
[4][LVDSPLL reg0]=[0x80000080]
[4][LVDSPLL reg1]=[0x800b89d8]
[4][LVDSPLL reg2]=[0x00000002]
[5][UNIVPLL reg0]=[0xfb003001]
[6][MMPLL   reg0]=[0xf0003700]
[7][ISPPLL  reg0]=[0x80004080]

********** pll_test help **********
enable  pll: echo enable  id [mod_name] > /proc/clkmgr/pll_test
disable pll: echo disable id [mod_name] > /proc/clkmgr/pll_test
~ #

~ # cat /proc/clkmgr/subsys_test
********** subsys register dump **********
[0][SYS_MD1]=[0x0000000d], state(0)
[1][SYS_MD2]=[0x0000000d], state(0)
[2][SYS_DPY]=[0x0000000d], state(1)
[3][SYS_DIS]=[0x0000000d], state(1)
[4][SYS_MFG]=[0x00001f12], state(0)
[5][SYS_ISP]=[0x00003f12], state(0)
[6][SYS_IFR]=[0x0000000d], state(1)
[7][SYS_VEN]=[0x0000ff12], state(0)
[8][SYS_VDE]=[0x0000ff12], state(0)
SPM_PWR_STATUS=0x0007e04c, SPM_PWR_STATUS_S=0x0007e04c

********** subsys_test help **********
enable subsys:  echo enable id > /proc/clkmgr/subsys_test
disable subsys: echo disable id [force_off] > /proc/clkmgr/subsys_test
~ #

~ # cat /proc/clkmgr/udelay_test

********** udelay_test help **********
test udelay:  echo delay > /proc/clkmgr/udelay_test
~ #