Merge pull request #79 from StanfordVLSI/mflowgen

Add preliminary top-level synthesis flow

.buildkite/pipeline.yml

@@ -1,31 +1,70 @@
 steps:
-  - command: |
+  - label: "test"
+    command: |
       # set up environment
       source /cad/modules/tcl/init/bash
-      module load base xcelium dc_shell
-      export DRAGONPHY_PYTHON=/usr/local/miniconda/bin/python3.7
+      module load base xcelium
       export DW_TAP=/cad/synopsys/syn/L-2016.03-SP5-5/dw/sim_ver/DW_tap.v
       export BUILD_VIEW=cpu
       printenv
 
+      # create virtual environment
+      /usr/local/miniconda/bin/python3.7 -m venv venv
+      source venv/bin/activate
+
       # run regression script
       source regress.sh
-    label: "test"
+
+      # deactivate virtual environment
+      deactivate
+    artifact_paths:
+      - "tests/new_tests/*/build/*.eps"
     timeout_in_minutes: 60
     agents:
       fault2: "true"
-  - command: |
+  - label: "test_mflowgen"
+    command: |
+      # set up environment
+      # modules loaded aim to match those used by Garnet
+      source /cad/modules/tcl/init/bash
+      module load base xcelium lc pts syn/latest genus innovus/19.10.000 icadv/12.30.712 calibre/2019.1
+      export BUILD_VIEW=asic
+      export DRAGONPHY_PROCESS=FREEPDK45
+      export FREEPDK45=/cad/freepdk/FreePDK45
+      printenv
+
+      # create virtual environment
+      /usr/local/miniconda/bin/python3.7 -m venv venv
+      source venv/bin/activate
+
+      # run mflowgen script
+      source mflowgen.sh
+
+      # deactivate virtual environment
+      deactivate
+    artifact_paths:
+      - "tests/new_tests/*/build/*.eps"
+    timeout_in_minutes: 60
+    agents:
+      fault2: "true"
+  - label: "test_emu"
+    command: |
       # set up environment
       source /etc/environment
-      export DRAGONPHY_PYTHON=python3.7
       export FPGA_SERVER=1
       export DW_TAP=/tools/synopsys/syn/L-2016.03-SP5-5/dw/sim_ver/DW_tap.v
       export BUILD_VIEW=fpga
       printenv
 
+      # create virtual environment
+      python3.7 -m venv venv
+      source venv/bin/activate
+
       # run regression script
       source regress.sh
-    label: "test_emu"
+
+      # deactivate virtual environment
+      deactivate 
     timeout_in_minutes: 60
     agents:
         fpga_verif: "true"

.gitignore

@@ -33,6 +33,8 @@ qrcTechFile*
 tcbn16*
 pnr/data
 pnr/gate_size_test
+flow/*/outputs
+designs/*/*/temp/
 
 #########################
 # other files to ignore #

designs/dragonphy_top/.mflowgen.yml

@@ -0,0 +1 @@
+construct: construct-commercial-full.py

designs/dragonphy_top/constraints/configure.yml

@@ -0,0 +1,44 @@
+# Adapted from Garnet
+
+name: constraints
+
+commands:
+  - python gen_constraints.py
+
+outputs:
+  - constraints.tcl
+
+parameters:
+  # time in ns and capacitance in pF
+
+  # Name of the design
+  design_name: undefined
+
+  # Main clocks in the design
+  clk_retimer_period: 0.7
+  clk_in_period: 0.7
+  clk_jtag_period: 100.0
+
+  # Retimer clock uncertainty
+  clk_retimer_setup_uncertainty: 0.03
+  clk_retimer_hold_uncertainty: 0.03
+
+  # JTAG clock uncertainty
+  clk_jtag_setup_uncertainty: 1.0
+  clk_jtag_hold_uncertainty: 0.03
+
+  # Capacitance and transition time
+  max_capacitance: 0.1
+  max_transition: 0.2
+  max_clock_transition: 0.1
+
+  # Clocks that can be monitored from analog_core
+  clk_hs_period: 0.25
+  clk_hs_transition: 0.025
+
+  # I/O delays and transitions
+  digital_input_delay: 0.05
+  digital_input_transition: 0.5
+  input_transition: 0.03
+  output_load: 0.02
+  output_delay: 0.7

designs/dragonphy_top/constraints/gen_constraints.py

@@ -0,0 +1,154 @@
+import os
+from pathlib import Path
+
+OUTPUT_FILE = 'constraints.tcl'
+
+e = os.environ
+output = f'''\
+# Modified from ButterPHY and Garnet constraints
+
+# Design constraints for synthesis
+# time unit : ns
+# cap unit: pF
+
+#########
+# Params
+#########
+
+# primary I/Os being treated as don't touch nets
+
+set analog_io {{ext_rx_inp ext_rx_inn ext_Vcm ext_Vcal ext_rx_inp_test \\
+               ext_rx_inn_test ext_clk_async_p ext_clk_async_n ext_clk_test0_p \\
+               ext_clk_test0_n ext_clk_test1_p ext_clk_test1_n ext_clkp \\
+               ext_clkn clk_out_p clk_out_n clk_trig_p clk_trig_n}}
+
+set analog_net [get_pins ibuf_*/clk]
+
+set primary_digital_inputs {{ext_rstb ext_dump_start jtag_intf_i.phy_tdi \\
+                            jtag_intf_i.phy_tck jtag_intf_i.phy_tms \\
+                            jtag_intf_i.phy_trst_n}}
+
+#########
+# Clocks
+#########
+
+create_clock -name clk_retimer -period {e["clk_retimer_period"]} [get_pins {{iacore/clk_adc}}]
+create_clock -name clk_in -period {e["clk_in_period"]} [get_ports ext_clkp]
+create_clock -name clk_jtag -period {e["clk_jtag_period"]} [get_ports jtag_intf_i.phy_tck]
+
+set_dont_touch_network [get_pins {{iacore/clk_adc}}]
+set_dont_touch_network [get_port jtag_intf_i.phy_tck]
+
+set_clock_uncertainty -setup {e["clk_retimer_setup_uncertainty"]} clk_retimer
+set_clock_uncertainty -hold {e["clk_retimer_hold_uncertainty"]} clk_retimer
+set_clock_uncertainty -setup {e["clk_jtag_setup_uncertainty"]} clk_jtag
+set_clock_uncertainty -hold {e["clk_jtag_hold_uncertainty"]} clk_jtag
+
+###########
+# Net const
+###########
+
+# This constraint causes a huge number of buffers to be inserted
+# set_max_capacitance {e["max_capacitance"]} [current_design]
+
+set_max_transition {e["max_transition"]} [current_design]
+set_max_transition {e["max_clock_transition"]} [all_clocks]
+
+set hs_nets [get_pins {{iacore/*pi_out_meas* iacore/*inbuf_out_meas* \\
+                       iacore/*pfd_inp_meas* iacore/*pfd_inn_meas* \\
+                       iacore/*del_out_pi*}}]
+
+foreach x [get_object_name $hs_nets] {{
+	create_clock -name clk_hs_net_$x -period {e["clk_hs_period"]} [get_pins $x]
+	set_max_transition {e["clk_hs_transition"]} [get_clocks clk_hs_net_$x]
+}}
+
+echo [all_clocks]
+
+###########
+# Analog nets
+###########
+
+set_dont_touch_network [get_ports $analog_io]
+set_dont_touch_network $analog_net
+set_dont_touch_network [all_outputs]
+
+###########
+# I/O const
+###########
+
+set_input_delay {e["digital_input_delay"]} [get_ports $primary_digital_inputs]
+set_input_transition {e["digital_input_transition"]} [get_ports $primary_digital_inputs]
+
+set_input_transition {e["input_transition"]} [all_inputs]
+set_load {e["output_load"]} [all_outputs]
+set_output_delay {e["output_delay"]} [all_outputs]
+
+############
+# False path
+############
+
+# asynchronous clock domains
+set_false_path -from clk_retimer -to clk_jtag
+set_false_path -from clk_jtag -to clk_retimer
+
+# top-level ports
+set_false_path -through [get_ports]
+
+# analog core
+set_false_path -through [get_pins -of_objects iacore]
+
+# digital core
+set_false_path -through [get_pins -of_objects idcore]
+
+# black box buffers
+set_false_path -through [get_pins -of_objects ibuf_async]
+set_false_path -through [get_pins -of_objects ibuf_main]
+set_false_path -through [get_pins -of_objects ibuf_test0]
+set_false_path -through [get_pins -of_objects ibuf_test1]
+
+################
+# Other options
+################
+
+# Make all signals limit their fanout
+set_max_fanout 20 {e["design_name"]}
+
+################
+# DONT USE CELLS
+################
+
+# foreach lib $mvt_target_libs {{
+#   set_dont_use [file rootname [file tail $lib]]/*D0BWP*
+# }}
+
+# Settings from Garnet to consider
+# (all commented out at the moment)
+
+# This constraint sets the input drive strength of the input pins of
+# your design. We specifiy a specific standard cell which models what
+# would be driving the inputs. This should usually be a small inverter
+# which is reasonable if another block of on-chip logic is driving
+# your inputs.
+
+# set_driving_cell -no_design_rule \\
+#  -lib_cell $ADK_DRIVING_CELL [all_inputs]
+
+# sr 02/2020
+# haha IOPAD cells already have dont_touch property but not ANAIOPAD :(
+# Without dont_touch, they disappear during dc-synthesis
+# set_dont_touch [ get_cells ANAIOPAD* ]
+
+# sr 02/2020
+# Arg turns out not all IOPAD cells have dont_touch property I guess
+# set_dont_touch [ get_cells IOPAD* ]
+'''
+
+# create output directory
+OUTPUT_DIR = Path('outputs')
+OUTPUT_DIR.mkdir(exist_ok=True, parents=True)
+
+# write output text
+with open(OUTPUT_DIR / OUTPUT_FILE, 'w') as f:
+    f.write(output)
+