Skip to content

Pull requests: SpinalHDL/SpinalHDL

New pull request New
28 Open 721 Closed
28 Open 721 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

StreamCCByToggle Altera attributes
#1543 opened Sep 19, 2024 by g0t00 Loading…
2 tasks
Fix the wrong directory when generating .lst of Verilog/SV
#1538 opened Sep 16, 2024 by Tikifire Loading…
Implement DDRx Controller by Bmb2Dfi
#1533 opened Sep 10, 2024 by liyaohou • Draft
1
Add Support for IPXACT 2022 and Vivado-Specific 2009 IP Core Packaging in Spinal
#1530 opened Sep 9, 2024 by ZhaokunHu Loading…
1 of 2 tasks
2
Fix FSM bug
#1529 opened Sep 7, 2024 by thajohns Loading…
1 task done
1
4
Add mill template link to readme
#1505 opened Aug 13, 2024 by mrcmry Loading…
2
Add SamplerCC pushCd(reg) -> popCd(BufferCC)
#1500 opened Aug 5, 2024 by Dolu1990 Loading…
set rst name for default clock domain by ClockDomainConfig
#1484 opened Jul 17, 2024 by yportne13 Loading…
1
RFC: Add blackboxing for simple 1-port synchronous ROMs
#1475 opened Jul 11, 2024 by bunnie Loading…
2 tasks
20
ACE & ACE-Lite support
#1450 opened Jun 12, 2024 by KireinaHoro • Draft
3 of 8 tasks
5
formal: add yosys+ghdl backend
#1429 opened May 30, 2024 by NikLeberg Loading…
5 tasks
53
Bugfix/wb pipelined
#1375 opened Mar 26, 2024 by jdavidberger Loading…
1
71
Ability to remap address for BusSlaveFactory
#1354 opened Mar 13, 2024 by KireinaHoro • Draft
2 tasks
14
Verilog generated when using synchronous resets is not understood by SymbiYosys - remove "assert() else begin end"-block generation for now
#1315 opened Feb 19, 2024 by janschiefer Loading…
1
TaggedUnion implementation
#1241 opened Nov 10, 2023 by ronan-lashermes Loading…
2 tasks
35
[feature] FuseSocGeneratorBuilder provide a easy way to use fusesoc
#1232 opened Nov 2, 2023 by chenbo-again Loading…
27
feat: add loadHex function for SparseMemory
#1015 opened Jan 12, 2023 by hanm2019 Loading…
1 of 2 tasks
1
6
Add ethernet udp tx/rx module feature ✨ Feature idea with clear API defined wontfix The issue would not be fixed
#1010 opened Jan 10, 2023 by jjyy-Huang Loading…
1 of 7 tasks
16
feature: add new optional reset signal to StreamWidthAdapter and StreamFragmentWidthAdapter
#1008 opened Jan 8, 2023 by jonnykl Loading…
2 tasks
6
Move tests
#1001 opened Dec 18, 2022 by numero-744 • Draft
4 tasks
1
25
feat: SpinalTestBench
#968 opened Nov 19, 2022 by numero-744 Loading…
2 tasks done
v1.8.1
@numero-744
100
feat: protocol simulation API; implemented for AHB
#879 opened Oct 3, 2022 by numero-744 • Draft
1
31
add combStage() to rename returned Stream
#749 opened May 24, 2022 by pwang7 • Draft
14
Memory: multiple ports with writeFirst should be permited.
#678 opened Apr 6, 2022 by nbstrike Loading…
6
[RFC] Add support for multiple CS pin for SDRAM controller
#577 opened Jan 10, 2022 by t123yh Loading…
1
ProTip! Type g i on any issue or pull request to go back to the issue listing page.