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Fix issue when inode file ID cannot be created #227

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@mjklemm mjklemm commented Dec 9, 2024

This PR fixes a problem when the file ID cannot be determined during code-gen to create a unique symbol name. This can happen when a preprocessor leaves a file name in the line tag that does not exist.

@mjklemm mjklemm added the flang label Dec 9, 2024
@mjklemm mjklemm self-assigned this Dec 9, 2024
@mjklemm mjklemm force-pushed the fix-missing-inode-id branch from 874778a to 7f75c76 Compare December 9, 2024 19:57
@mjklemm mjklemm changed the title Fix issue when inode file ID cannot be created. Fix issue when inode file ID cannot be created Dec 9, 2024
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Thank you Michael, this looks good to me. I think we should add a unit test for it, though. Passing the input MLIR through stdin to mlir-translate should trigger this (e.g. cat test.mlir | mlir-translate -mlir-to-llvmir - | FileCheck test.mlir).

@mjklemm mjklemm force-pushed the fix-missing-inode-id branch from 7f75c76 to b03a052 Compare January 12, 2025 18:14
arsenm and others added 20 commits March 6, 2025 09:13
…lvm#128034)

This provides a range to decide how to subdivide the vector register
budget on gfx90a+. A single value declares the minimum AGPRs that
should be allocatable. Eventually this should replace amdgpu-no-agpr.

I want this primarily for testing agpr allocation behavior. We should
have a heuristic try to detect a reasonable number of AGPRs to keep
allocatable.
This performs the minimal replacment of amdgpu-no-agpr to
amdgpu-agpr-alloc=0. Most of the test diffs are due to the new
attribute sorting later alphabetically.

We could do better by trying to perform range merging in the attributor,
and trying to pick non-0 values.
According to the commit history, the constructors removed by LWG4140
have never been added to libc++.

Existence of non-public or deleted default constructor is observable,
this patch tests that there's no such default constructor at all.
Forked from llvm/test/CodeGen/AArch64/arm64-ld1.ll

Incorrectly handled by handleUnknownInstruction:
- llvm.aarch64.neon.ld1x2, llvm.aarch64.neon.ld1x3,
llvm.aarch64.neon.ld1x4
- llvm.aarch64.neon.ld2, llvm.aarch64.neon.ld3, llvm.aarch64.neon.ld4
- llvm.aarch64.neon.ld2lane, llvm.aarch64.neon.ld3lane,
llvm.aarch64.neon.ld4lane
- llvm.aarch64.neon.ld2r, llvm.aarch64.neon.ld3r, llvm.aarch64.neon.ld4r
…rCreator.

ExecutionSession can provide the Triple, so this argument has been redundant
for a while, and no in-tree clients use it.
In order for the union APFloat::Storage to permit access to the
semantics field when another union member is stored there, all members
of Storage must be standard layout. This is not necessarily the case
for DoubleAPFloat which may be non-standard layout because there is no
requirement that its std::unique_ptr member is standard layout. Fix this
by converting Floats to a raw pointer.

Reviewers: arsenm

Reviewed By: arsenm

Pull Request: llvm#129981
…king..."

This reverts commit f905bf3 while I fix
some compile errors reported on the buildbots (see e.g.
https://lab.llvm.org/buildbot/#/builders/53/builds/13369).
The StringRef overload is often error-prone as users might forget to
register the MCSymbol.

Add comments to MCTargetExpr and MCSymbolRefExpr::VariantKind.
In the distant future the VariantKind parameter might be removed.
…th fixes.

This re-applies f905bf3, which was reverted in
c861c1a due to compiler errors, with a fix for
MLIR.
)

This extension adds thirty eight  bit manipulation instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6

This patch adds assembler only support.

Co-authored-by: Sudharsan Veeravalli <[email protected]>
llvm#129980)

We used to filter out relocations corresponding to NOP+ADR instruction
pairs that were a result of linker "relaxation" optimization. However,
these relocations will be useful for reversing the linker optimization.
Keep the relocations and ignore them while symbolizing ADR instruction
operands.
llvm#129234)

This is the second attempt to bring initial support for [[assume()]] in
the Clang Static Analyzer.
The first attempt (llvm#116462) was reverted in
2b9abf0 due to some weird failure in a
libcxx test involving `#pragma clang loop vectorize(enable)
interleave(enable)`.

The failure could be reduced into:
```c++
template <class ExecutionPolicy>
void transform(ExecutionPolicy) {
  #pragma clang loop vectorize(enable) interleave(enable)
  for (int i = 0; 0;) { // The DeclStmt of "i" would be added twice in the ThreadSafety analysis.
    // empty
  }
}
void entrypoint() {
  transform(1);
}
```

As it turns out, the problem with the initial patch was this:
```c++
for (const auto *Attr : AS->getAttrs()) {
  if (const auto *AssumeAttr = dyn_cast<CXXAssumeAttr>(Attr)) {
    Expr *AssumeExpr = AssumeAttr->getAssumption();
    if (!AssumeExpr->HasSideEffects(Ctx)) {
      childrenBuf.push_back(AssumeExpr);
    }
  }
  // Visit the actual children AST nodes.
  // For CXXAssumeAttrs, this is always a NullStmt.
  llvm::append_range(childrenBuf, AS->children()); // <--- This was not meant to be part of the "for" loop.
  children = childrenBuf;
}
return;
 ```

The solution was simple. Just hoist it from the loop.

I also had a closer look at `CFGBuilder::VisitAttributedStmt`, where I also spotted another bug.
We would have added the CFG blocks twice if the AttributedStmt would have both the `[[fallthrough]]` and the `[[assume()]]` attributes. With my fix, it will only once add the blocks. Added a regression test for this.

Co-authored-by: Vinay Deshmukh <vinay_deshmukh AT outlook DOT com>
nikic and others added 26 commits March 7, 2025 09:45
Some lldb tests from llgs category fail on RISC-V target due to lack of
necessary condition checks. This patch adapts these tests by taking into
account the peculiarities of the RISC-V architecture
…lvm#130114)

Very similar to object pointer assignment, the difference is the SSA
types of the LHS (!fir.ref<!fir.boxproc<()->()>> and RHS
(!fir.boxproc<()->()).

The RHS must be saved as simple address, not descriptors (it is not
possible to make CFI descriptor out of procedure entity).
Works fine on macos, so expand the tested hosts. This should work
on windows too, but it's been a pain debugging the error on the bot.
…) -> shuffle(concat(x,x),concat(y,y),m3) on VBMI targets (llvm#130134)

With VBMI we are guaranteed to support cross-lane 256-bit shuffles, so subvector splats should always be cheap.

Fixes llvm#116931
Clang already removes parsed enumerators when merging typedefs to
anonymous enums. This is why the following example decl used to be
handled correctly while merging, and ASTWriter behaves as expected:

```c
typedef enum { Val } AnonEnum;
```
However, the mentioned mechanism didn't handle named enums. This leads
to stale declarations in `IdResolver`, causing an assertion violation in
ASTWriter ``Assertion `DeclIDs.contains(D) && "Declaration not
emitted!"' failed`` when a module is being serialized with the following
example merged enums:

```c
typedef enum Enum1 { Val_A } Enum1;
enum Enum2 { Val_B };
```

The PR applies the same mechanism in the named enums case.

Additionally, I dropped the call to
`getLexicalDeclContext()->removeDecl` as it was causing a wrong
odr-violation diagnostic with anonymous enums.

Might be easier to to review commit by commit. Any feedback is
appreciated.

### Context

This fixes frontend crashes that were encountered when certain
Objective-C modules are included on Xcode 16. For example, by running
`CC=/path/to/clang-19 xcodebuild clean build` on a project that contains
the following Objective-C file:

```c
#include <os/atomic.h>

int main() {
  return memory_order_relaxed;
}
```
This crashes the parser in release, when ASTReader tries to load the
enumerator declaration.
…#130050)

S_PREFETCH_* instructions may cause host to terminate process in case of
the invalid address.

Co-authored-by: Stanislav Mekhanoshin <[email protected]>
We try to only use X32 for gnux32 triple

Noticed while reviewing llvm#106555
…gy` (llvm#128885)

This replaces the `-prefer-intrinsic-cost` and
`type-based-intrinsic-cost` flags with a single
`-intrinsic-cost-strategy=<strategy>` flag.

The possible strategies are:

 * `instruction-cost`
   - Use TargetTransformInfo::getInstructionCost()
 * `intrinsic-cost`
   - Use TargetTransformInfo::getIntrinsicInstrCost()
 * `type-based-intrinsic-cost`
   - Calculate the intrinsic cost based only on argument types
The tests updated by this commit are expected to fail when targetting a
darwin platform. As they rely on target detection based on the host,
this is currently checked by using the `XFAIL: system-darwin`
annotation.

This approach becomes a problem when trying to run such tests on a
cross-compiling build of clang on a darwin platform. When no darwin
targets are included in the build, the XFAIL will still apply even
though the target used is not related to the darwin platform, and the
tests will unexpectedly pass.

To fix this issue, this patch updates the condition used by the tests'
XFAIL annotation to `target={{.*}}-darwin{{.*}}`, ensuring they only are
xfailed when the relevant target is used.
…lvm#129692)

Enable the LLVM_ENABLE_RUNTIMES=flang-rt build of the Fortran runtime
for the amdgpu-offload-* buildbots. This pre-population cmake cache
files is referred to by the llvm-zorg annotated builder factory
[script](https://github.com/llvm/llvm-zorg/blob/872f477610d83821c9f1368c969006789b21011b/zorg/buildbot/builders/annotated/amdgpu-offload-cmake.py#L26).

The corresponding change in llvm-zorg is
llvm/llvm-zorg#402
and collect telemetry about a command's execution.

*NOTE: Please consider this PR a DRAFT ( Waiting on PR/127696 to be
submitted. )

---------

Co-authored-by: Jonas Devlieghere <[email protected]>
Previously an extra block was created by splitting the previous exit
block. This produced incorrect results when the outlined region
statically never terminated because then there wouldn't be a valid exit
block for the outlined region, this caused this newly added block to
have an incoming edge from outside of the outlining region, which caused
outlining to fail.

So far as I can tell this extra block no longer serves any purpose. The
comment says it is supposed to collate multiple control flow edges into
one place, but the code as it is now does not achieve this. In fact, as
can be seen from the changes to lit tests, this block was not actually
outlined in the end. This is because there are actually two code
extractors: one in the callback for creating a parallel op which is used
to find what the input/output variables are (which does have this block
added to it), and another one which actually does the outlining (which
this block was not added to).

Tested with the gfortran and fujitsu test suites.

Fixes llvm#112884
…#125686)

Codegen for AArch64 16/32/64-bit floating-point atomic read-modify-write
operations (`atomicrmw {fadd,fmin,fmax}`) using LD{B}FADD, LD{B}FMAX and
LD{B}FMIN atomic instructions.
…fload-*" (llvm#130274)

Reverts llvm#129692

The builder amdgpu-offload-rhel-8-cmake-build-only fails because its
version of Ninja is too old. At least Ninja 1.10 is required for its
support for dependencies between Fortran modules.

https://lab.llvm.org/buildbot/#/builders/204/builds/2696
Passed precheck before 844a1d5
started deleting the dead instructions
@mjklemm mjklemm force-pushed the fix-missing-inode-id branch from b03a052 to 4136395 Compare March 11, 2025 13:31
@mjklemm mjklemm closed this Mar 11, 2025
@mjklemm mjklemm deleted the fix-missing-inode-id branch March 11, 2025 13:31
@mjklemm mjklemm restored the fix-missing-inode-id branch March 11, 2025 13:31
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