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Feedback #1
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Feedback #1
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@stevehoover I approved the changes but I'm not sure that was what you wanted. |
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Excellently-commented code. Well done up through slide 37.
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// opcode is stored in $instr[6:0] (page 16) | ||
// but since the first 2 bits are always 1 we simply ignore them | ||
// ==? TL-VERILOG feature to compare with a "don't care (x)" value |
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(technically, it's a SystemVerilog feature)
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Ok thanks for the feedback 🙂
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Subscribed: @jmevel