My solutions to the workshop exercises

This repository contains my solutions: a calculator and a RISC-V implementation. See below for information and links about the workshop.

My RISC-V has all the features explained in the workshop - pipelines, jumps, loads and stores (full word only). The design worked both in Makerchip and when flashed on a real FPGA (provided in the workshop). It passed all 4 test case files included in the workshop.

Be warned that the quality of the code probably isn't the greatest, as it was my first project in any hardware description language.

RISC-V_MYTH_Workshop

For students of "Microprocessor for You in Thirty Hours/THree weeks" (MYTH) Workshop, offered by Redwood EDA and training partners VLSI System Design (VSD) and The EEView.

About the Workshop

This workshop has recieved a great deal of attention in the RISC-V community for enabling students to learn at a pace never before possible through the use of TL-Verilog and Makerchip. Some links:

• Workshop info
• riscv.org blogs about 13-year-old Nicholas Sharkey and 12-year-old Niel Josiah
• Linkedin posts
• riscv.org's maintains a list of RISC-V cores, including MYTH cores