Skip to content

RHTome/Password-validation

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

11 Commits
 
 
 
 

Repository files navigation

Password-validation

verilog HDL

Implement password verification on FPGA board equiped with 4×4 keyboard using verilog HDL. Only when the sequence of numbers entered is the same as the password set, the circuit output a signal indicating that the input is correct.

About

verilog HDL

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published